No abstract

Tungsten thin films were selectively deposited onto silicon surfaces by a low pressure chemical vapor deposition process utilizing, sequentially, silicon reduction and then hydrogen reduction of WF6. Surface selectivity and conformal coverage of microelectronic structures is demonstrated. X-ray diffraction and Auger analysis indicate the films are well crystallized, with the possibility of a fraction of a percent oxygen content. The room-temperature resistivity is ∼18 μΩ cm, composed of residual and intrinsic contributions of 12 and 6 μΩ cm, respectively. The Hall effect indicates the material is predominantly a hole conductor, with a relatively low Hall mobility that is consistent with the large residual resistivity. Difficulties with a simple interpretation of the Hall effect are discussed.

The Auger electron spectrum induced by the impact of 100-keV Ar+ on metallic aluminum is shown to be consistent with the source of Auger electrons being ejected target particles. The principal spectral line has been identified as being due to ejected Al atoms with a single 2p vacancy. Subsidiary peaks are due to ejected atoms and Al+ ions with one or two 2p vacancies. The ion-induced Auger spectrum of silicon is similar. By contrast the spectrum induced by Ar+ impact on Be exhibits a rather broad peak characteristic of a K-shell vacancy and is similar to that induced by the impact of electrons. By considering the lifetime of the Be K-shell vacancy we conclude that the Auger decay occurs while the Be atoms are either in the solid or interacting with the surface.

No abstract

A bipolar structure with an estimated f~ of 5 GHz is fabricated on a selective epitaxial layer. A shallow buried layer (0.25 pm-0.50 pm) is formed by diffusing arsenic atoms from an arsenic implanted polysilicon layer. The polysilicon layer is removed by converting it to oxide and etching the oxide. The defective regions at the edges of the selective epitaxial layer are removed by a plasma etch step to form defect-free basecollector junctions; the junctions can be placed less than 2 p m from the edges without degrading the device characteristics. Using the selective epitaxial growth, LOCOS isolation, and the shallow buried layer, semi-dielectric transistor isolation is achieved.