Bump shear is widely used to characterize the interfacial strength of Cu/low-k structures. In this paper, the blanket low-k structure was used to evaluate the reliability and strength of Cu/low-k structures based on experiment and finite-element modeling technique. The objectives of this paper are to determine the critical stress parameters for low-k interfaces with different low-k structures, to understand the failure mechanism, and to improve low-k structure reliability by optimizing some parameters. In this paper, a comprehensive parametric study was carried out. Such parameters include the effect of three different low-k structures, high-Pb solder bump versus Pb-free solder bump, different underbump metallization (UBM) thicknesses, barrier-layer material elastic modulus, and shear ram height on low-k structure reliability. The simulation findings can be summarized as follows. The critical stress decreases with the number of layers of low-k structure. An Sn-Ag solder bump results in a higher shear force and stress than a high-Pb solder bump. Reducing the UBM thickness can help improve the low-k structure reliability.

This paper presents the study on the effect of low κ stacked layer, chip pad design structures, and shift pad design of a large die size Cu/low κ (BD ™ ) chip for improving assembly and reliability performance on organic buildup substrate FCBGA (FlipChip Ball Grid Array). Bump shear characterization has been performed on the integrity of different stacked layer and pad structure, supported by bump shear modeling analysis. Initial reliability testing was performed on assembled package to identify the best choice of design and finally implemented on the reliability test vehicle for verification. In addition, a potential chip crack problem due to excessive warpage in FCBGA with large die assembly is examined and a simple failure criterion is proposed.

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