Molecular beam epitaxy and scanning tunneling microscopy (STM) patterning are combined to form highly doped, planar devices in silicon at the atomic level. The absolute device location is registered to microscopic markers (see image; scale bar: 50 μm) for the alignment of surface contacts, enabling the correlation of the electrical properties of atomically controlled devices such as nanowires, tunnel junctions, and nanodots to the dopant location, monitored using high‐resolution STM techniques.

Three-dimensional (3D) control of dopant profiles in silicon is a critical requirement for fabricating atomically precise transistors. We demonstrate conductance modulation through an atomic scale 3 nm wide δ-doped silicon-phosphorus wire using a vertically separated epitaxial doped Si:P top-gate. We show that intrinsic crystalline silicon grown at low temperatures (∼250 °C) serves as an effective gate dielectric permitting us to achieve large gate ranges (∼2.6 V) with leakage currents below 1 pA. Combining scanning tunneling lithography for precise lateral confinement, with monolayer doping and low temperature epitaxial overgrowth for precise vertical confinement, we can realize multiple layers of nano-patterned dopants in a single crystal material. These results demonstrate the viability of highly doped, vertically separated epitaxial gates in an all-crystalline architecture with long-term implications for monolithic 3D silicon circuits and for the realization of atomically precise donor architectures for quantum computing.

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