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A 300 V power switch using planar n-channel DMOS and p-channel pinched resistance transistors to switch dynamically currents of 300 mA will be presented here. SummaryHandling high power is usually reserved to vertically structured discrete components, as they are superior to lateral structures with respect to the achievable power density and on-resistance. Yet, the big advantage of the coplanar approach is the possi¬ bility of integration. A high voltage CMOS technology compatible with a low voltage CMOS process has been developed. Figure 1 shows a cross-section of the high voltage n-and p-channel transistors. Using a conventional CMOS-output stage with symme¬ trical, static supply voltages, the power which can be handled is rather limited. Figure 2 shows for the positive part of the output voltage, that the power dissipation during rise and fall-2 time At is Cr*Vr /2At (1). The shaded area indicates the voltage drop across the activated transistor with on-resistance R. Assu¬ ming a maximum allowable power dissipation of 3 watts on chip (dual-in-1ine package) and a duty cycle of K9 one finds with (1) the relationship between maximum supply voltage and maximum fre¬ quency in figure 3. Further the break-down voltage of the out¬ put transistor has to be higher than the total output voltage swing being twice the supply voltage in this case. In order to handle more power another circuitry and (or) signal handling is required« A solution is indicated in figure 4. The main idea is, that the dissipated power on chip is kept as low as possible by making the pulses with the required duty cycle and rise-and fall-times off chip and switching them, if necessary, on chip to the output. So the average voltage drop across the activated tran¬ sistor (Rnn=R) can be kept smaller than with static supply voltage. Figure 4 shows for the positive part of the output voltage that a reduction in the power disspiation by the term 2-r/At can be expected (x«At). During the high voltage pulse a capaci¬ tive voltage divider Cj, C2 creates the gate-source voltage V6S» which is necessary to turn the output stage on (C,, C? are available as parasitic capacitances). See the curves with num¬ ber 1. Rising the gate potential by a précharge signal Vo, V._ G5 is kept below the threshold voltage VT and the output tran¬ sistor remains in the off state: See the curves with number 2.Optimizing the capacitive voltage divider Cj, C2 and the pré¬ charge voltage Vq a low voltage input controllability (<20 V) can be achieved. Here the précharge voltage V has been taken symmetrical (curves 1', 2). In this way it is possible to handle more peak power on chip than with static supply voltages. For example: A total swing of 300 V is obtained at 200 pF capacitive load with rise-and fall-times of 100 nsec during which the out¬ put transistors have to withstand only half of the total output voltage swing. Figure 5 shows a microphotograph of the CMOS power switch.