The Scalable Processor-Independent Design for Electromagnetic Resilience (SPIDER) is a new family of fault-tolerant architectures under development at NASA Langley Research Center (LaRC). The SPIDER is a general-purpose computational platform suitable for use in ultrareliable embedded control applications. The design scales from a small configuration supporting a single aircraft function to a large distributed configuration capable of supporting several functions simultaneously.

In a joint project with the FAA, NASA Langley is developing a hardware design in accordance with RTCA DO-254: Design Assurance Guidance for Airborne Electronic Hardware. The purpose of the case study is to gain understanding of the new guidance document and generate an example suitable for use in training.

No abstract

The design and development of a closed-loop system to study and evaluate the performance of a Recoverable Computer System (RCS) in high intensity electromagnetic environments (EME) is presented. A linearized model of the B737 autoland sequence running in real-time was chosen for this study, with the RCS executing the autopilot control laws and a personal computer (PC) running a model of the B737 aircraft. A Windows-based software package running on the PC was developed to handle the communication of data and commands between the RCS and the flight simulation. A MATLAB simulation model was used to analyze the recovery technique and determine potential performance improvements by proper selection of the recovery mechanism parameters. The performance results of the RCS and characteristics of its upset recovery scheme while exercising flight control laws under ideal conditions as well as in the presence of electromagnetic fields are also discussed.

A prototype fault-tolerant clock synchronization system is designed t o a proven correct formal specification. T h e specification is derived from Schneider's general paradigm for Byzantine resilient clock synchronization. One addition to the formal theory is a mechanism for proven recovery from a bounded number of transient faults. A description of a four-clock implementation which satisfies the requirements of the formal theory is presented. In addition, the design provides options for initialization which enable recovery from some correlated transient failures. Extra logic is included to provide experimental control of these options. Simulation results are presented.