Articles you may be interested inFabrication of curved structures with electron-beam and surface structure characterization

25-nm-wide lines and spaces have been fabricated in 22.5-nm-thick films of PdAu (40 : 60) using electron-beam exposure and polymethylmethacrylate (PMMA) resist. A high-resolution scanning transmission electron microscopy (STEM) was used to expose the resist and the samples were mounted on 60-nm-thick Si3N4 membrane substrates. Previously, the smallest metal structures formed with a resist process were 60 nm wide with spaces between the lines several times larger than the lines. The results presented here show that 25-nm lines can be fabricated with a center to center spacing of 50 nm.

Abstract

A high-resolution electron beam has been used to generate metal structures 8 nm wide and 10 nm high using ’’contamination’’ resist and dense metal patterns with 25 nm linewidths on 50-nm centers using PMMA resist. These resist materials together with standard deposition techniques and ion beam milling have been used to prepare a variety of structures on the order of nanometers in dimension. Present metal structure dimensions are limited by electron backscattering events in the substrate, the microstructure of the metallic thin film, and unknowns in the contamination resist process itself. The processing techniques are discussed as well as the preparation of substrates which are almost transparent to the electron beam.

This paper describes a method of optimally sizing digital circuits on a static-timing basis. All paths through the logic are considered simultaneously and no input patterns need be specified by the user. The method is unique in that it is based on gradient-based, nonlinear optimization and can accommodate transistor-level schematics without the need for pre-characterization. It employs efficient time-domain simulation and gradient computation for each channel-connected component. A large-scale, general-purpose, nonlinear optimization package is used to solve the tuning problem. A prototype tuner has been developed that accommodates combinational circuits consisting of parameterized library cells. Numerical results are presented.