The small-signal equivalent circuit of AlGaN/GaN HEMT is discussed It is shown that an extremely high gate voltage has to be applied to correctly determine series resistances. Effects appearing at high forward gate voltages are discussed. Good agreement between measured and simulated data has been achieved.

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ABSTRACT

The increasing demand for DRAM capacity and performance in computing, and especially servers, has led to the development of a new memory-interface standard, the fully buffered DIMM (FB-DIMM).FB-DIMMs can host up to 36 DRAMs whose communication to the host processor is facilitated by the advanced memory buffer (AMB). While DRAMs on a DIMM interact with their respective AMB using the conventional DDR2 standard, the AMB sends to and receives data from the host processor or a neighboring FB-DIMM by means of differential point-to-point signaling.In this paper, the implementation details of data recovery and retiming of the AMB serial links are discussed. The chip comprises 24 serial links, a core processing unit, and a DDR interface. To support an 800Mb/s DDR2 data rate, links must operate at 4.8Gb/s. FB-DIMMs are connected in a daisy-chain configuration, and as such, the serial links function as repeaters; they recover and retime data, process, and forward data to the next DIMM, starting from and ending at the host processor. Figure 18.6.1 depicts the block diagram of a single high-speed lane including the CDR, electrical idle, the IQ-generator, a retiming FIFO, and the transmitter.The FB-DIMM protocol uses electrical idle (EI) as the primary mechanism to initialize, control state transitions, and to enter and exit the disable state. AMB enters EI when both the differential (DM) and the common-mode (CM) levels of the received data on at least two of three assigned links are low.The key challenge with the EI-detection circuit is its required resolution and bandwidth. The EI must detect the valid, but deteriorated differential levels (±80mV) of serial data in the presence of considerable CM noise both in EI and active modes; and with fast response time, it must determine whether the incoming data stream is valid or if the preceding AMB is in idle state. Figure 18.6.2 is a simplified schematic of the EI circuit illustrating only the differential level detection. CMFB biases the gates of draincoupled devices, Md+ and Md-near V t when DM=0. With the application of a differential data stream, Md+ and Md-gates alternate above V t . Acting as a wideband full-wave rectifier, the pair generates a current, Iint, which is in turn dc-averaged by the RC load to effect a voltage drop on Vint. Replica biasing produces VintR to which Vint is compared in order to indicate entry into or exit from EI. As seen from the figure, though the input instantaneous voltage level in the active mode is frequently below that of EI, the circuit never makes a false transition, and achieves entry and exit detection times of 16ns and 8ns over PVT and mismatch, outperforming the specification of 60ns and 30ns [1].A half-rate (2.4GHz) CML clock is distributed to pairs of lanes and is used to generate, by means of a polyphase filter (Fig. 18.6.3), quadrature clocks that drive two adjacent phase interpolators (PIs). Worst case IQ error is 0.015UI, or 3ps, and duty-cycle error is less than 0.5%. Phase interpolation is achieved by quadrant-based phase-mixing...