We investigated the effects of quantum confinement in determining the interface traps (Dit) and border traps (Nbt) of ALD deposited Al2O3 with temperature variations onto InxGa1-xAs on a 300mm Si (001) substrate. We also analysed the impact of these effects on the total gate capacitance of highk/Si and high-k/InxGa1-xAs structures using 1D Poisson-Schrodinger solver simulation tool (Nextnano). While quantum confinement has no or very little impact on the gate capacitance of high-k/Si structure, it has a considerably high amount of impact on the high-k/InxGa1-xAs structures and substantially lowers the total gate capacitance. To reflect the actual thickness between the insulator-semiconductor interface and charge centroid, capacitance-equivalent-thickness was used to reflect the effects of quantum confinement in the InxGa1-xAs layer. The Dit and Nbt values extracted using capacitance-equivalent-thickness were observed to be around 10% and 25%, respectively, higher than the values of extraction with equivalent-oxidethickness. INDEX TERMS Interface trap density, border trap density, quantum mechanical effect, high-k, III-V substrate.

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The characteristics of traps between the Al0.25Ga0.75N barrier and the GaN channel layer in a high-electron-mobility-transistors (HEMTs) were investigated. The interface traps at the Al0.25Ga0.75N/GaN interface as well as the border traps were experimentally analyzed because the Al0.25Ga0.75N barrier layer functions as a dielectric owing to its high dielectric constant. The interface trap density Dit and border trap density Nbt were extracted from a long-channel field-effect transistor (FET), conventionally known as a FATFET structure, via frequency-dependent capacitance–voltage (C–V) and conductance–voltage (G–V) measurements. The minimum Dit value extracted by the conventional conductance method was 2.5 × 1012 cm−2·eV−1, which agreed well with the actual transistor subthreshold swing of around 142 mV·dec−1. The border trap density Nbt was also extracted from the frequency-dependent C–V characteristics using the distributed circuit model, and the extracted value was 1.5 × 1019 cm−3·eV−1. Low-frequency (1/f) noise measurement provided a clearer picture of the trapping–detrapping phenomena in the Al0.25Ga0.75N layer. The value of the border trap density extracted using the carrier-number-fluctuation (CNF) model was 1.3 × 1019 cm−3·eV−1, which is of a similar level to the extracted value from the distributed circuit model.

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We presented an explicit empirical model of the thermal resistance of AlGaN/GaN high-electron-mobility transistors on three distinct substrates, including sapphire, SiC, and Si. This model considered both a linear and non-linear thermal resistance model of AlGaN/GaN HEMT, the thickness of the host substrate layers, and the gate length and width. The non-linear nature of channel temperature—visible at the high-power dissipation stage—along with linear dependency, was constructed within a single equation. Comparisons with the channel temperature measurement procedure (DC) and charge-control-based device modeling were performed to verify the model’s validity, and the results were in favorable agreement with the observed model data, with only a 1.5% error rate compared to the measurement data. An agile expression for the channel temperature is also important for designing power devices and monolithic microwave integrated circuits. The suggested approach provides several techniques for investigation that could otherwise be impractical or unattainable when utilizing time-consuming numerical simulations.