We present a simple, effective, and controllable method to uniformly thin down the thickness of as-exfoliated two-dimensional Bi2O2Se nanoflakes using Ar+ plasma treatment. Atomic force microscopy (AFM) images and Raman spectra indicate that the surface morphology and crystalline quality of etched Bi2O2Se nanoflakes remain almost unaffected. X-ray photoelectron spectra (XPS) indicate that the O and Se vacancies created during Ar+ plasma etching on the top surface of Bi2O2Se nanoflakes are passivated by forming an ultrathin oxide layer with UV O3 treatment. Moreover, a bottom-gate Bi2O2Se-based field-effect transistor (FET) was constructed to research the effect of thicknesses and defects on electronic properties. The on-current/off-current (I on/I off) ratio of the Bi2O2Se FET increases with decreasing Bi2O2Se thickness and is further improved by UV O3 treatment. Eventually, the thickness-controlled Bi2O2Se FET achieves a high I on/I off ratio of 6.0 × 104 and a high field-effect mobility of 5.7 cm2 V–1 s–1. Specifically, the variation trend of the I on/I off ratio and the electronic transport properties for the bottom-gate Bi2O2Se-based FET are well described by a parallel resistor model (including bulk, channel, and defect resistance). Furthermore, the I ds–V gs hysteresis and its inversion with UV irradiation were observed. The pulsed gate and drain voltage measurements were used to extract trap time constants and analyze the formation mechanism of different hysteresis. Before UV irradiation, the origin of clockwise hysteresis is attributed to the charge trapping/detrapping of defects at the Bi2O2Se/SiO2 interface and in the Bi2O2Se bulk. After UV irradiation, the large anticlockwise hysteresis is mainly due to the tunneling between deep-level oxygen defects in SiO2 and p++-Si gate, which implies the potential in nonvolatile memory.

We have engineered pH sensitivity of graphene-based ion-sensitive field-effect transistors (ISFETs) by applying plasma treatment on graphene with two different plasma sources, CF4 and O2 plasma. The CF4 plasma treatment, leaving F-terminated sites on graphene, results in a lower sensitivity of 23 mV/pH, while the O2 plasma treatment, leaving O-terminated sites, results in a higher sensitivity of 40 mV/pH. The validity of the aforementioned plasma treatments on graphene was confirmed by Raman spectra and X-ray photoelectron spectroscopy (XPS). Both plasma-treated graphene samples exhibit good stability with low drift and a small hysteresis width in measuring the pH of the solution, resulting from the two-dimensional (2D) feature of graphene. Finally, a reference-less ISFET that comprises two graphene films with different engineered sensitivities was demonstrated. Both engineered graphene films are directly exposed to the electrolyte solution, with the CF4-treated graphene replacing the reference electrode and the O2-treated graphene as the sensing layer. As surface potentials of the two films are opposite in sign, this device exhibits an overall sensitivity as the difference in sensitivities (i.e., 14.5 mV/pH) of the two individual films. More importantly, the long-term drift behaviors of the two films also cancel each other and the drift rate reaches as low as 0.38 mV/h for this reference-less device. This approach brings opportunities for future high-performance 2D-based ISFETs with extremely low drift and high stability.

The p-type transparent semiconductor CuI has a high potential to be used in thin film transistors (TFTs) due to high hole mobility and solution processability. However, the lower copper vacancy formation energy and the subsequent high hole concentration in CuI lead to a low on/off current ratio (ION/IOFF) for CuI TFT devices. The density functional theory results suggest that the copper vacancy formation energy increases with the CuBr content in the Br-doped CuI film, resulting in lower hole concentration. Alloying CuI with CuBr is proposed to reduce the hole concentration in the CuIBr alloy. The CuIBr TFTs with Br content ranging from 0% to 10% were fabricated using the solution method. It is found that the hole mobility decreases from 8 to 1 cm2 V−1 s−1, while the ION/IOFF ratio increases from 102 to 104 with the increasing Br content. The CuIBr TFT with 7.5% Br content exhibits a high hole mobility larger than 5 cm2 V−1 s−1 and high ION/IOFF ratio of 104, which paves the way for inorganic-based CMOS circuits on flexible and transparent substrates.

The in-memory logic computing has been intensively studied as being considered as an important scenario to address the power-consumption issue posed by modern computers based on the von Neumann architecture. However, the realization of in-memory logic computing is generally based on memristors prepared by vacuum techniques and the implementation of logic operation requires multiple cycles of voltage pulses, which limits the computing efficiency. In addition, the logic architectures that cannot be mapped into large crossbar arrays restrict the level of parallelism. A CuI memristor is prepared by a solution-based process in this work. Based on the CuI memristor arrays, with delicately designed implement strategy, a set of logic operations can be implemented with one single cycle of voltage pulses, demonstrating the high efficiency. Moreover, all proposed logic architectures are able to be mapped to large memristor crossbar arrays directly, demonstrating the great potentials in computations with high degree of parallelism. Owing to the reconfigurable property, a one-bit full adder is realized by cascading the memristor-based logic gates. CuI, high parallelism, in-memory computing, logic gate, memristor. INDEX TERMS