Harnessing parity–time symmetry with balanced gain and loss profiles has created a variety of opportunities in electronics from wireless energy transfer to telemetry sensing and topological defect engineering. However, existing implementations often employ ad hoc approaches at low operating frequencies and are unable to accommodate large-scale integration. Here we report a fully integrated realization of parity–time symmetry in a standard complementary metal–oxide–semiconductor process technology. Our work demonstrates salient parity–time symmetry features such as phase transition as well as the ability to manipulate broadband microwave generation and propagation beyond the limitations encountered by existing schemes. The system shows 2.1 times the bandwidth and 30% noise reduction compared to conventional microwave generation in the oscillatory mode, and displays large non-reciprocal microwave transport from 2.75 to 3.10 GHz in the non-oscillatory mode due to enhanced nonlinearities. This approach could enrich integrated circuit design methodology beyond well-established performance limits and enable the use of scalable integrated circuit technology to study topological effects in high-dimensional non-Hermitian systems.

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Recent works propose neural network-(NN-) inspired analog-to-digital converters (NNADCs) and demonstrate their great potentials in many emerging applications. These NNADCs often rely on resistive random-access memory (RRAM) devices to realize the NN operations and require high-precision RRAM cells (6∼12-bit) to achieve a moderate quantization resolution (4∼8-bit). Such optimistic assumption of RRAM resolution, however, is not supported by fabrication data of RRAM arrays in large-scale production process. In this paper, we propose an NN-inspired super-resolution ADC based on low-precision RRAM devices by taking the advantage of a co-design methodology that combines a pipelined hardware architecture with a custom NN training framework. Results obtained from SPICE simulations demonstrate that our method leads to robust design of a 14-bit super-resolution ADC using 3bit RRAM devices with improved power and speed performance and competitive figure-of-merits (FoMs). In addition to the linear uniform quantization, the proposed ADC can also support configurable high-resolution nonlinear quantization with high conversion speed and low conversion energy, enabling future intelligent analog-to-information interfaces for nearsensor analytics and processing.