This paper presents design for testability of FFT IIFFT IP core with CAD tools. As demanding market require ever more complex, faster and denser circuits, high quality tests become essential to meet design specifications in terms of reliability, time-to-market, costs, etc. No solution other than design-for-test can achieve acceptab le fault to detect physical fails for highly integrated systems. Within this context, an overview and analysis of existing test methods is given in this paper. And the architecture of FFT is introduced and appropriate test methods are chosen to realize design for test of FFT/IFFT IP core. As a result, the design with high fault coverage needing less test time is achieved.