An inherently nonlinear relation between the output current of the tetralateral position sensitive detector (PSD) and the position of the incident light spot has been found theoretically. Based on single-chip microcomputer and the theoretical relation between output current and position, a new signal processor capable of correcting nonlinearity and reducing position measurement deviation of tetralateral PSD was developed. A tetralateral PSD (S1200, 13×13mm2, Hamamatsu Photonics K.K.) was measured with the new signal processor, a linear relation between the output position of the PSD, and the incident position of the light spot was obtained. In the 60% range of a 13×13mm2 active area, the position nonlinearity (rms) was 0.15% and the position measurement deviation (rms) was ±20μm. Compared with traditional analog signal processor, the new signal processor is of better compatibility, lower cost, higher precision, and easier to be interfaced.

In this study, an area-efficient 8-channel 128-point fast Fourier transform (FFT) processor is proposed for IEEE 802.11ac standard MIMO-OFDM system. The proposed FFT processor is based on mixed-radix multi-path delay commutator (MRMDC) architecture and supports eight spatial data streams. Using input memory array transpose architecture and a bit-reversal circuit, the proposed FFT processor can generate eight input and output spatial data streams in natural order. Therefore, the processor can be used directly in MIMO-OFDM systems without additional input or output RAM. The proposed FFT processor is designed using hardware description language and synthesized to a gate-level circuit using a TSMC 90-nm CMOS standard cell library. Compared with other 8-channel MRMDC FFT processors, the proposed FFT processor can reduce the logic gate count of the MRMDC module by approximately 12.5 %.Keywords 802.11ac · Fast Fourier transform (FFT) · Multiple-input multipleoutput (MIMO) · Orthogonal frequency-division multiplexing (OFDM) · Mixed-radix multi-path delay commutator (MRMDC)

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This paper presents design for testability of FFT IIFFT IP core with CAD tools. As demanding market require ever more complex, faster and denser circuits, high quality tests become essential to meet design specifications in terms of reliability, time-to-market, costs, etc. No solution other than design-for-test can achieve acceptab le fault to detect physical fails for highly integrated systems. Within this context, an overview and analysis of existing test methods is given in this paper. And the architecture of FFT is introduced and appropriate test methods are chosen to realize design for test of FFT/IFFT IP core. As a result, the design with high fault coverage needing less test time is achieved.