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This paper presents the design of a low power LNA with second stage that uses a notch filter for DS-UWB application. The LNA employs a current reuse structure to reduce the power consumption and an active second order notch filter to produce band rejection in the 5 -6 GHz frequency band. The input reflection coefficient S11 and output reflection S22 are both less than -10 dB. The maximum power gain S21 is 15 dB while the maximum rejection ratio is over -10 dB at 4.8 GHz. The minimum noise figure is 5 dB. The input referred third-order intercept point (IIP3) is -7 dBm at 6 GHz. The power consumption is 6.4 mW from a 1-V power supply.

This paper presents research on a low power CMOS UWB LNA based on a cascoded common source and current-reused topology. A systematic approach for the design procedure from narrow band to UWB is developed and discussed in detail. The power reduction can be achieved by using body biased technique and current-reused topology. The optimum width of the major transistor device M1 is determined by the power-constraint noise optimization with inner parasitic capacitance between the gate and source terminal. The derivation of the signal amplification S21 by high frequency small signal model is displayed in the paper. The optimum design of the complete circuit was studied in a step by step analysis. The measurements results show that the proposed circuit has superior S11, gain, noise figure, and power consumption. From the measured results, S11 is lower than −12 dB, S22 is lower than −10 dB and forward gain S21 has an average value with 12 dB. The noise figure is from 4 to 5.7 dB within the whole band. The total power consumption of the proposed circuit including the output buffer is 4.6 mW with a supply voltage of 1 V. This work is implemented in a standard TSMC 0.18 µm CMOS process technology.