Breast cancer is a common to females worldwide. Today, technological advancements in cancer treatment innovations have increased the survival rates. Many theoretical and experimental studies have shown that a multiple classifier system is an effective technique for reducing prediction errors. This study compared the particle swarm optimizer (PSO) based artificial neural network (ANN), the adaptive neuro-fuzzy inference system (ANFIS), and a case-based reasoning (CBR) classifier with a logistic regression model and decision tree model. It also applied three classification techniques to the Mammographic Mass Data Set, and measured its improvements in accuracy and classification errors. The experimental results showed that, the best CBR-based classification accuracy is 83.60%, and the classification accuracies of the PSO-based ANN classifier and ANFIS are 91.10% and 92.80%, respectively.

This paper proposes an optimal design of the linear channel prediction scheme for LTE-A uplink transmission, taking into account the effect of channel estimation errors. The optimization criterion is to minimize mean square prediction errors, averaged over the distributions of true channel coefficients and estimation errors. We derive a closed-form solution of the optimal channel predictor and provide exact analysis for the achievable mean square error (MSE). The performance gain, in terms of the amount of reduction in MSE, as compared with the conventional channel predictor, is also analytically characterized. Simulation results are used to validate our MSE analyses and to confirm the performance advantage of the proposed solution.

Reliability issues are very important especially for the highvoltage (HV) devices. Unfortunately, an HV nLDMOS is often damaged by a latch-up (LU) problem when it triggered by a transient noise and a bias condition VDDmax is greater than that of the device holding-voltage (Vh). The snapback phenomena of the new adding adaptive layers in the source/drain ends of an nLDMOS are investigated in this paper. It is a novel method to reduce the surface field, control the trigger voltage and holding voltage. Experimentally, the right-shifting characteristic of snapback I-V curves depends on new adding Pad, LPad, Nad, and LNad parameters, respectively. Eventually, these source/drain adaptive layers of an nLDMOS can effectively improve the LU immunity under an HV operation.

This paper deals with a detailed study of ESD failure modes, failures distribution and how to strengthen of the VDMOS ICs used for power applications. The ESD post-zapped failure of power VDMOS ICs due to HBM, MM, and CDM stresses are examined in this work. Through standard failure analysis techniques by using EMMI and SEM were applied to identify the failure locations. It is found that the ESD robustness is VESD(HBM) > VESD(MM) > VESD(CDM) for these non-ESD protected DUTs. Meanwhile, the ESD failure sites will be closed to the gate bonding pad as with a positive zapping and higher dV/dt pulse such as in CDM testing. And, the failure mappings have been studied to establish the difference in damaged features of HBM, MM, and CDM. Furthermore, the ESD protection designs of power VDMOS ICs are also addressed in this work. The first ESD incorporated design is Zener diodes back-to-back clamping the gate-to-source pad, and on the other hand, another one excellent design contains two Zener diodes clamping the gate-to-source and gate-to-drain terminals of a VDMOS, respectively.