The paper presents a novel transpose path metric (TPM) algoritluii to rcduce tlie interconnection routing complexity for ~1 d i x -2 ~ Viterbi decoder. With simple local interconnections, the algorithm can provide a permutation function for state rcarrangenient in a transpose strategy. With features of modulation and regularity, this algorithm is v e n suitable for VLSI implementation; consequently, a larger memory Icngth VA decoder can be constructed with several siiiallcr mciiiory length modules Finally, a VLSI architecture for 16-states radix-4 VA decoder using TPM lias been developed.

In this paper, we present a rad1x-2~ Viterbi decoding with Transpose Path Metric (TPM) processor. The TPM processor can provide a permutation function for state rearrangement with simple local interconnection.For interconnection realization, the routing complexity is less than that of the delay-commutator reported previously. In addition, a higher memory length Viterbi processor can be constructed with lower radix-2k modules. With features of modulation and cell regularity, the r a d i ~-2 ~ Viterbi decoding with TPM processor is very suitable for VLST implementation,