In this work, we study the access (read and write) scheme of the newly proposed Multi-Level Cell Spin-Transfer Torque Random Access Memory (MLC STT-RAM) from both the circuit design and architectural perspectives. Based on the physical principles of the resistance state transition of MLC STT-RAM, we proposed a read circuitry based on Dichotomic search algorithm and three write schemes with various design complexities -simple, complex, and hybrid schemes. The circuit and architectural level evaluations were conducted to analyze the power and performance tradeoffs in each proposed write mechanisms of MLC STT-RAM.

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The ability to evaluate high frequency writer performance is crucial to the write-head designs for high data rate application. To quantify the write-head performance at high frequency (∼1 GHz), a new high frequency detection approach has been implemented. The essence of the method is to utilize a two-step signal mixing process to produce the force harmonics, which are not only proportional to the amplitude of the deep-gap field but also fall within the active bandwidth of the probe spectrum. Furthermore, a dual-vibration detection scheme is also described, which can provide superior high spatial resolution and enhance the sensitivity of attractive mode force microscopy as well at high frequencies.

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