This paper proposes a 60 GHz quadrature PLL frequency synthesizer for the IEEE802.15.3c with wide tuning range and low phase noise. The synthesizer is constructed using a 20 GHz PLL that is coupled with a Quadrature Injection Locked Oscillator (QILO) as a frequency tripler to generate the 60 GHz signal. The 20 GHz PLL generates a signal with a phase noise that is lower than dBc/Hz using tail feedback to improve the phase noise while having a 17% tuning range. The proposed 60 GHz QILO uses a combination of parallel and tail injection to enhance the locking range by improving the QILO injection efficiency at the moment of injection and has a 12% tuning range. Both the 20 GHz PLL and the QILO were fabricated as separate chips using a 65 nm CMOS process and measurement results show a phase noise that is less than 95 dBc/Hz@1 MHz at 60 GHz while consuming 80 mW from a 1.2 V supply. To the author's knowledge this phase noise is about 20 dB better than recently reported QPLLs and about 10 dB compared to differential PLLs operating at a similar frequency and at a similar offset.

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A method for shortening of the settling time in all digital phase-locked loops is proposed. The method utilizes self monitoring to obtain the parameters necessary for feed-forward compensation. Analysis shows that by employing this technique both fast settling and good stability can be achieved simultaneously. Matlab and Verilog-AMS simulation shows that typical settling speed can be reduced to less than one tenth compared to a system without the feed-forward compensation, by merely employing the feed-forward compensation system. Further more a design example shows that this settling time can be decreased further to less than one fifteenth through design considerations when compared to a speed optimized phase-locked loop design system without direct reference feed-forward compensation.

Abstract-A method of direct input reference feed-forward compensation is proposed and discussed for all digital phase locked loop based synthesizers. The practical issues in implementing the system are addressed, and analysis of the feed-forward estimation error on the system is performed. A sample model was created and simulated. Simulation shows the effect of the feed-forward estimation error on the system's settling speed. The system was shown to be able to reduce the settling time to one eighth of the minimum achievable settling speed of a system without feed forward compensation.