Analysis and Design of Direct Reference Feed-Forward Compensation for Fast-Settling All-Digital Phase-Locked Loop

Abstract

A method for shortening of the settling time in all digital phase-locked loops is proposed. The method utilizes self monitoring to obtain the parameters necessary for feed-forward compensation. Analysis shows that by employing this technique both fast settling and good stability can be achieved simultaneously. Matlab and Verilog-AMS simulation shows that typical settling speed can be reduced to less than one tenth compared to a system without the feed-forward compensation, by merely employing the feed-forward compensation system. Further more a design example shows that this settling time can be decreased further to less than one fifteenth through design considerations when compared to a speed optimized phase-locked loop design system without direct reference feed-forward compensation.

Fine and wide frequency tuning digital controlled oscillators utilizing capacitance position sensitivity in distributed resonators

“…Aside from its advantages of having less process, voltage and temperature (PVT) dependence it also allows such techniques as direct frequency modulation [1,2], and allows ease of implementation of fast settling techniques such as dynamic filter bandwidth control [3], and direct reference feed-forwarding method [4,5].…”

Enhanced Acquisition and Tracking in All Digital Phase-Locked Loops

“…The effects of varying DPLL design parameters on timing jitter have been investigated in [23] to obtain minimum output jitter. In [5] a technique for achieving fast settling and good stability in all digital phase-locked loops has been proposed which utilizes self-monitoring to obtain the parameters necessary for feedforward compensation. The jitter reduction approach taken in [20] and [7] is based on making a modification to symbol timing error detection algorithms of [11] and [25], respectively, to reduce the level of jitter for M-PSK signals.…”

“…(1) Estimation of the jitter [21,29] (2) Selection of the loop design parameters [5,23] (3) Modification of the detector [7,20] (4) Dynamic modification of the loop gain [2] (5) Modification of the loop filter [6,8].…”