This paper presents a deterministic diagnosis analysis method for hold-time faults in scan chains. The defects discussed in this paper are primarily seen at low Vdd values, so called Vdd-min defects; Vdd -max defects can also be a problem. Traditional approaches require data collection, the creation of additional patterns, and an iterative trip back to the tester. This is a time consuming process and does not always lead to a closed end solution. This paper also presents a method to detect multiple hold-time faults in the chain using auto generated pattern, real-time on the tester. The approach includes validation of the hold-time fault model, characterization of the failure behavior in terms of Vdd and data dependencies and finally localization to a cone of logic including the data paths and the clock trees. This method of hold-time localization is organized into three steps. First, the chain integrity test is run at the safe voltage. Second, a set of new patterns is created and run at the failing voltage. Finally, the data is shifted out and compared with the simulation result. The data provides the locations of all of the hold-time faults for the selected failing voltage. Combined with silicon voltage probing, the technique allows the analysis to localize the faults and to measure timing slack on sub-nets in the failing circuitry. This allows very close correlation between timing models and silicon performance leading to more robust design/process matching.

We have designed a new current-mode low-voltage, low-power supply, high-frequency CMOS VCO(Vo1tage Controlled Oscillator) circuit. The main purpose of this new circuit is to obtain low phase noise with more than 1 GHz oscillation frequency from one battery cell. The fully differential-type voltage clamp delay cell VCO enables extremely low supply voltage operation due to wide tuning range and superior linearity between the oscillator frequency and control voltage of a ring oscillator because of low phase noise. A design which combines the transitions of each delay cell output enables the VCOs high frequency operation. The characteristics of the designed VCO were examined by the HSPICE and SABER circuit simulation. Operation with a 3.3 power supply and 3.6 GHz oscillation frequency was verified.

Same output frequencies at each DUT of the testing circuit are multiplied by different LO frequencies signals at mixers stages, which different fr equency-translated spectrums were captured at capture port simultaneously for achieving fully parallel test ofRF device.~-20 ]