Cu gap-fill is enhanced by replacing the conventional Ta liner with a Co liner in a 22 nm width interconnect structure. The improvement with Co liner seen at the line-end area is attributed to a better resputtered Cu seed profile, which is thicker and exhibits no agglomeration compared to that on Ta liner. The mechanism of Co offering better Cu seed coverage than Ta was further studied and determined to be associated with its better wetting and higher sticking coefficient with Cu during the resputtering process. Similar gap-fill performance was also demonstrated with a reflow Cu seed process. The initial highly conformal Cu seed coverage profile on Co helps ensure a uniform Cu reflow process within the interconnect structure, therefore providing better top-open dimension for electrochemical plating process compared to reflow Cu seed on Ta. . This paper is part of the JES Focus Issue on Electrochemical Processing for Interconnects.As advanced microelectronics move toward the 20 nm node and beyond, back-end of line (BEOL) interconnects are shrinking to sub-80 nm pitch dimensions. 1 Driving toward smaller pitch encounters numerous integration challenges, including Cu metallization. From a circuit performance perspective, one particular issue is the increase of Cu line resistance (R). As metal line widths approach and even become smaller than the electron mean free path within Cu, line resistance no longer linearly scales with dimension. Instead, Cu resistivity starts to increase dramatically due to the increased electron surface scattering. 2 The subsequent increase of the RC (resistance × capacitance) delay within the interconnect circuit will negatively impact the circuit speed. Meanwhile, higher R will also consume more energy and complicate heat dissipation, both of which are not ideal for low-power devices.Besides metallization-related performance challenges, another critical issue in these fine lines is reliability, particularly electromigration (EM). It is increasingly difficult to control microstructure within the metal line and as well as interface qualities at fine dimension. Cu microstructure does not easily form a bamboo grain structure by grain growth from electrochemical plated (ECP) Cu overburden in sub-40 nm metal widths. 3 Connected grain boundaries within polycrystalline Cu lines could act as fast Cu diffusion paths. 4 Meanwhile, the other two critical interfaces, Cu-liner and Cu-cap, need to maintain their strong bonding for EM extendibility. 5,6 But before these performance and reliability issues can even be considered, first these sub-40 nm wide dual-damascene structures must be metallized without Cu-voiding defects. The conventional approach for metallization is to first deposit a layer of barrier and liner (usually TaN and Ta, correspondingly), followed by a Cu seed. The coated wafer will go into a plating bath with ECP Cu nucleation initiated on the PVD Cu seed surface first, and then be filled bottom-up with Cu ECP process. Bottom-up growth results from faster ECP Cu growth at the feature bo...

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