In this work, we prepared one kind of metallic golden wafer coated with tantalum/tantalum nitride (Ta/TaN) films or single Ta film by either PVD (Physical Vapor Deposition ) process or ALD (Atomic layer deposition) process to alleviate the charge accumulation and mitigate the electrostatic enhanced impurity adsorption. Through this approach, the charging effect on line CD measurement is effectively eliminated. We compared the charging effect among normal wafer, metallic golden wafer, and the evaluated golden wafer’s life time in terms of charging effect prevention by means of a long-term test. Moreover, to extend the lifetime of golden wafer, a rework process was investigated to deoxidize the surface oxidation layer and prevent it from the charging induced long-term performance degradation. For CD-SEM stability control, we designed a daily monitor flow utilizing the golden wafer to ensure and maintain a healthy CDSEM condition for in-line product measurement. Finally, we extended the concept of this metallic golden wafer into other potential metrology related applications such as CD-SEM tool matching and calibration.

LWR (line width roughness) is normally defined as the 3 sigma of critical dimension (CD) variation along a segment of a line. As CDs of semiconductor devices continue to be scaled down, LWR, the looming critical index, needs to be well controlled within 8% of gate line CD for advanced logic technology nodes as ITRS states. In this contribution, we mainly focused on the gate etch solution to reduce post-gate etch LWR including PPT (pre-plasma treatment), post-Barc (bottom anti-reflective coating) treatment (cure) and plasma induced polymer formation (coating). Besides, we also leveraged the uniform design experiment (UDE) to investigate the impact of Barc/Cure/Darc (dielectric anti-reflective coating) open steps on LWR and identified the optimal Barc/Darc condition among 25 UDE pi-runs. Finally, we obtained the optimal gate etch condition which achieved 2.8nm (the strictest CD-SEM algorithm ever reported) overall LWR performance including both low frequency and high frequency components), roughly more than >30% LWR improvement compared to the initial photoresist LWR. As implant has been reported to be the only way to reduce the low frequency LWR for photoresist, LWR improvement from various implant species and doping levels, the side-effects of implantation and its potential contribution to the overall improvement of post-etch LWR are also addressed.

OCD metrology has been proven to be a fast, accurate, and non-destructive knob for in-situ monitoring of line width and profile. In order to main Moore's law, device dimension is moving towards 45nm technology node and beyond, it is becoming increasingly difficult to perform the in-situ evaluation for those complicated structures by either CD-SEM or AFM. In this work, we come up with one specific 3D pattern to realize the 3D monitoring of p-MOS silicon recess (PSR) etch performance. The corresponding OCD library was identified and implemented on Nova OCD 3090 next. Several key floating parameters include PSR & STI depth, gate & AA CD, nitride spacer width and SWA. Good CD correlation between OCD and CD-SEM is obtained on the same 3D pattern. Consistent trench depth match is also observed between OCD and blanket pattern based AFM. Besides, dynamic repeatability test shows the acceptable reliability for 3D PSR OCD monitoring as well.

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