The fabrication of sigma-shaped silicon recess normally consists of dry etch process to shape the silicon trench and post etch treatment to form the sigma-shaped cavity within bulk silicon substrate. Here we are dedicated to the optimization of silicon recess dry etch process and its effect on the final sigma-shaped SiGe physical performance. Results show the isotropic ratio of horizontal over vertical direction could be doubled. This caters much larger process window for the desired strain introduction at the hetero-junction of SiGe/Si. Besides, the corresponding dry etching solutions are also disclosed from the point of view of tip depth adjustment and tip horizontal pull-back control. Both physical indexes could be independently controlled to deliver the required sigma-shaped Si recess trench.

The strict shape control of sigma-shaped silicon trench has to leverage the dry etch process coupled with the appropriate post-etch treatment (PET). Here we addressed the strong link between the shape of dry etch based silicon recess and its effect on the definition of final sigma-shaped trench. Experiment results indicate the critical physical parameters of final sigma-shape silicon trench could be predicted by means of geometry analysis and monitoring dry etching related recess in bulk silicon. Besides, we also noticed the effect of pattern-dependent depth loading at dense areas. Organic polymer generated during etch process tends to introduce the trench depth variation. Polymer lean etch process has been proven as one of effective knobs to overcome such loading to some extent. In addition, the oxidation capacity of post-etch treatment can not be ignored. The ultra-thin silicon oxide film on silicon trench sidewall must be completely removed by dilute hydrofluoric acid before PET to avoid the possible trench depth loading.

OCD metrology has been proven to be a fast, accurate, and non-destructive knob for in-situ monitoring of line width and profile. In order to main Moore's law, device dimension is moving towards 45nm technology node and beyond, it is becoming increasingly difficult to perform the in-situ evaluation for those complicated structures by either CD-SEM or AFM. In this work, we come up with one specific 3D pattern to realize the 3D monitoring of p-MOS silicon recess (PSR) etch performance. The corresponding OCD library was identified and implemented on Nova OCD 3090 next. Several key floating parameters include PSR & STI depth, gate & AA CD, nitride spacer width and SWA. Good CD correlation between OCD and CD-SEM is obtained on the same 3D pattern. Consistent trench depth match is also observed between OCD and blanket pattern based AFM. Besides, dynamic repeatability test shows the acceptable reliability for 3D PSR OCD monitoring as well.

LWR (line width roughness) is normally defined as the 3 sigma of critical dimension (CD) variation along a segment of a line. As CDs of semiconductor devices continue to be scaled down, LWR, the looming critical index, needs to be well controlled within 8% of gate line CD for advanced logic technology nodes as ITRS states. In this contribution, we mainly focused on the gate etch solution to reduce post-gate etch LWR including PPT (pre-plasma treatment), post-Barc (bottom anti-reflective coating) treatment (cure) and plasma induced polymer formation (coating). Besides, we also leveraged the uniform design experiment (UDE) to investigate the impact of Barc/Cure/Darc (dielectric anti-reflective coating) open steps on LWR and identified the optimal Barc/Darc condition among 25 UDE pi-runs. Finally, we obtained the optimal gate etch condition which achieved 2.8nm (the strictest CD-SEM algorithm ever reported) overall LWR performance including both low frequency and high frequency components), roughly more than >30% LWR improvement compared to the initial photoresist LWR. As implant has been reported to be the only way to reduce the low frequency LWR for photoresist, LWR improvement from various implant species and doping levels, the side-effects of implantation and its potential contribution to the overall improvement of post-etch LWR are also addressed.

Optical Critical Dimension (OCD) metrology is a much popular and efficient way to monitor structure sizes such as heights, side wall angles (SWAs), and critical dimensions (CDs). Due to the continuous shrinkage of feature sizes, the IC process is becoming more and more complicated. The growing demand on the OCD applications always outpaces the development of OCD-technology capabilities. Thus, we have to find a more reliable method and a special structure to certify the capability of OCD modeling and library stability, so as to improve the measurement performance as much as possible. In this paper, we selected a 2-D Sigma Shape PMOS Silicon Recess (Σ-PSR) structure for the OCD modeling evaluation and established a certification procedure as well as a relevant evaluation method, which includes the design of DOE (Design of Experiment) wafers, the handbook for data collections, the scoreboard for OCD result analysis for verifying both OCD 2-D modeling performance and library stability. The DOE wafers were processed to form different PSR structures such as total silicon recess depth, sigma height, pull back, tip-off-gate, undercut, and spacer width splits, etc. There are 17-output required parameters for the OCD modeling. At least, 9 floating parameters are necessary to build the Σ-PSR model. The accuracy of the DOE trend and the precision, stability, and GRR (Gauge Repeatability and Reproducibility) of all output parameters were analyzed to evaluate the capability of the OCD modeling. TEM data were also collected to demonstrate the OCD performance of Σ-PSR profile monitor. Finally, we summarized the evaluation method and discussed the future OCD certification work by advanced reference metrology tools.