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Liquid crystalline (LC) organic semiconductors having long-range-ordered LC phases hold great application potential in organic field-effect transistors (OFETs). However, to meet real device application requirements, it is a prerequisite to precisely pattern the LC film at desired positions. Here, a facile method that combines the technique of inkjet printing and melt processing to fabricate patterned LC film for achieving high-performance organic integrated circuits is demonstrated. Inkjet printing controls the deposition locations of the LC materials, while the melt processing implements phase transition of the LC materials to form high-quality LC films with large grain sizes. This approach enables to achieve patterned growth of high-quality 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C 8 -BTBT) LC films. The patterned C 8 -BTBT LC film-based 7 × 7 OFET array has 100% die yield and shows high average mobility of 6.31 cm 2 V −1 s −1 , along with maximum mobility up to 9.33 cm 2 V −1 s −1 . As a result, the inverters based on the patterned LC films reach a high gain up to 23.75 as well as an ultrahigh noise margin over 81.3%. Given the good generality of the patterning process and the high quality of the resulting films, the proposed method paves the way for high-performance organic integrated devices.

The quest for organic field-effect transistors (OFETs) with low operating voltage has become highly compelling in many application areas, such as medical sensors, radio frequency identification (RFID), wearable and stretchable technologies, etc. To this end, considerable efforts have been devoted to decreasing the operation voltage of OFETs while retaining high performance over the last few decades. This Review focuses on the recent progress in the field of low-voltage OFETs. The critical factors to realize low-voltage OFETs are analyzed systematically through establishing the relationships between the operation voltage and subthreshold swing. Further on the strategic approaches for lowering the operation voltage, increasing gate dielectric capacitance, reducing the trap density within the semiconductor layer or at device interfaces, and using the negative capacitor effect, are summarized and discussed. We conclude with an overview of these critical methods and the key challenges to enable the laboratory-to-production transition.

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