It is of great significance to utilize CO2 as feedstock to synthesize biobased products, particularly single cell protein (SCP) as the alternative food and feed. Bioelectrochemical system (BES) driven by clean electric energy has been regarded as a promising way for Cupriavidus necator to produce SCP from CO2 directly. At present, the key problem of growing C. necator in BES is that reactive oxygen species (ROS) generated in cathode chamber are harmful to bacterial growth. Therefore, it is necessary to find a solution to mitigate the negative effect of ROS. In this study, we constructed a number of C. necator strains displayed with superoxide dismutase (SOD), which allowed the decomposition of superoxide anion radical. The effects of promoter and signal peptide on cell surface display with SOD were analyzed. The protein displayed on the surface was further verified by the fluorescence experiment. Finally, the growth of C. necator CMS incorporating a pBAD-SOD-E-tag-IgAβ plasmid could achieve 4.9 ± 1.0 of OD600 by 7 days, equivalent to 1.7 ± 0.3 g/L dry cell weight (DCW), and the production rate was 0.24 ± 0.04 g/L/d DCW, around 2.7-fold increase than the C. necator CMS with surface display (1.8 ± 0.3 of OD600). This study can provide an effective and novel strategy of cultivating strains for the production of CO2-derived SCP or other chemicals in BES.

The rapid development of remote sensing technology has brought about a sharp increase in the amount of remote sensing image data. However, due to the satellite’s limited hardware resources, space, and power consumption constraints, it is difficult to process massive remote sensing images efficiently and robustly using the traditional remote sensing image processing methods. Additionally, the task of satellite-to-ground target detection has higher requirements for speed and accuracy under the conditions of more and more remote sensing data. To solve these problems, this paper proposes an extremely efficient and reliable acceleration architecture for forward inference of the YOLOX-s detection network an on-orbit FPGA. Considering the limited onboard resources, the design strategy of the parallel loop unrolling of the input channels and output channels is adopted to build the largest DSP computing array to ensure a reliable and full utilization of the limited computing resources, thus reducing the inference delay of the entire network. Meanwhile, a three-path cache queue and a small-scale cascaded pooling array are designed, which maximize the reuse of on-chip cache data, effectively reduce the bandwidth bottleneck of the external memory, and ensure an efficient computing of the entire computing array. The experimental results show that at the 200 MHz operating frequency of the VC709, the overall inference performance of the FPGA acceleration can reach 399.62 GOPS, the peak performance can reach 408.4 GOPS, and the overall computing efficiency of the DSP array can reach 97.56%. Compared with the previous work, our architecture design further improves the computing efficiency under limited hardware resources.