Controlling the crystal quality and growth orientation
of high
performance III–V compound semiconductor nanowires (NWs) in
a large-scale synthesis is still challenging, which could restrict
the implementation of nanowires for practical applications. Here we
present a facile approach to control the crystal structure, defects,
orientation, growth rate and density of GaAs NWs via a supersaturation-controlled
engineering process by tailoring the chemical composition and dimension
of starting Au
x
Ga
y
catalysts. For the high Ga supersaturation (catalyst diameter
< 40 nm), NWs can be manipulated to grow unidirectionally along
⟨111⟩ with the pure zinc blende phase with a high growth
rate, density and minimal amount of defect concentration utilizing
the low-melting-point catalytic alloys (AuGa, Au2Ga, and
Au7Ga3 with Ga atomic concentration > 30%),
whereas for the low Ga supersaturation (catalyst diameter > 40
nm),
NWs are grown inevitably with a mixed crystal orientation and high
concentration of defects from high-melting-point alloys (Au7Ga2 with Ga atomic concentration < 30%). In addition
to the complicated control of processing parameters, the ability to
tune the composition of catalytic alloys by tailoring the starting
Au film thickness demonstrates a versatile approach to control the
crystal quality and orientation for the uniform NW growth.
A metal-cluster-decoration approach is utilized to tailor electronic transport properties (e.g., threshold voltage) of III-V NWFETs through the modulation of free carriers in the NW channel via the deposition of different metal clusters with different work function. The versatility of this technique has been demonstrated through the fabrication of high-mobility enhancement-mode InAs NW parallel FETs as well as the construction of low-power InAs NW inverters.
Single GaAs nanowire photovoltaic devices were fabricated utilizing rectifying junctions in the Au–Ga catalytic tip/nanowire contact interface. Current-voltage measurements were performed under simulated Air Mass 1.5 global illumination with the best performance delivering an overall energy conversion efficiency of ∼2.8% for a nanowire of 70 nm in diameter. As compared with metal contacts directly deposited on top of the nanowire, this nanoscale contact is found to alleviate the well-known Fermi-level pinning to achieve effective formation of Schottky barrier responsible for the superior photovoltaic response. All these illustrate the potency of these versatile nanoscale contact configurations for future technological device applications.
Due to the unique physical properties, small bandgap III-V semiconductor nanowires such as InAs and InSb have been extensively studied for the next-generation high-speed and high-frequency electronics. However, further CMOS applications are still limited by the lack of efficient p-doping in these nanowire materials for high-performance p-channel devices. Here, we demonstrate a simple and effective in situ doping technique in the solid-source chemical vapor deposition of InSb nanowires on amorphous substrates employing carbon dopants. The grown nanowires exhibit excellent crystallinity and uniform stoichiometric composition along the entire length of the nanowires. More importantly, the versatility of this doping scheme is illustrated by the fabrication of high-performance p-channel nanowire field-effect-transistors. High electrically active carbon concentrations of ~7.5 × 10(17) cm(-3) and field-effect hole mobility of ~140 cm(2) V(-1) s(-1) are achieved which are essential for compensating the electron-rich surface layers of InSb to enable heavily p-doped and high-performance device structures. All these further indicate the technological potency of this in situ doping technique as well as p-InSb nanowires for the fabrication of future CMOS electronics.
A simple and effective technique is presented to left shift the Dirac point of graphene transistors to induce n-type doping via the thermal decoration of Al nanoparticles. The versatility of this approach is illustrated by the fabrication of air-stable n-type doping in graphene devices with the improved on/off current ratio.
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