An electrochemical device capable of manifesting reversible charge storage at the interface of an active layer offers formidable advantages, such as low switching energy and long retention time, in realizing synaptic behavior for ultralow power neuromorphic systems. Contrary to a supercapacitor-based field-effect device that is prone to low memory retention due to fast discharge, a solid electrolyte-gated ZnO thin-film device exhibiting a battery-controlled charge storage mechanism via mobile charges at its interface with tantalum oxide is demonstrated. Analysis via cyclic voltammetry and chronoamperometry uniquely distinguishes the battery behavior of these devices, with an electromotive force generated due to polarization of charges strongly dependent on the scan rate of the applied voltage. The Faradaic-type diffusion-controlled charge storage mechanism exhibited by these devices is capable of delivering robust enhancement in the channel conductance and leads to a superior ON-OFF ratio of 10-10. The nonvolatile behavior of the interface charge storage and slow diffusion of ions is utilized in efficiently emulating spike timing-dependent plasticity (STDP) at similar time scales of biological synapses and unveils the possibility of STDP behavior using multiple in-plane gates that alleviate additional requirement of waveform-shaping circuits.

Negative capacitance transistors are a unique class of switches capable of operation beyond the Boltzmann limit to realize subthermionic switching. To date, the negative capacitance effect has been predominantly attributed to devices employing an unstable insulator with ferroelectric properties, exhibiting a two-well energy landscape, in accordance with the Landau theory. The theory and operation of a solid electrolyte field effect transistor (SE-FET) of subthreshold swing less than 60 mV/dec in the absence of a ferroelectric gate dielectric are demonstrated in this work. Unlike ferroelectric FETs that rely on a sudden switching of dipoles to achieve negative capacitance, we demonstrate a distinctive mechanism that relies on the accumulation and dispersion of ions at the interfaces of the oxide, leading to a subthreshold slope (SS) as low as 26 mV/dec in these samples. The frequency of operation of these unscaled devices lies in a few millihertz because at higher or lower frequencies, the ions in the insulator are either too fast or too slow to produce voltage amplification. This is unlike Landau switches, where the SS remains below 60 mV/dec even under quasi-static sweep of the gate bias. The proposed FETs show a higher on-current with a thicker oxide in the entire range of gate voltage, clearly distinguishing their scaling laws from those of ferroelectric FETs. Our theory, validated with experiment, demonstrates a new class of devices capable of negative capacitance that opens up alternate methods of steep switching beyond the traditional approach of ferroelectric or memristive FETs.

The processing of sequential and temporal data is essential to computer vision and speech recognition, two of the most common applications of artificial intelligence (AI). Reservoir computing (RC) is a branch of AI that offers a highly efficient framework for processing temporal inputs at a low training cost compared to conventional Recurrent Neural Networks (RNNs). However, despite extensive effort, two-terminal memristor-based reservoirs have, until now, been implemented to process sequential data by reading their conductance states only once, at the end of the entire sequence. This method reduces the dimensionality, related to the number of signals from the reservoir and thereby lowers the overall performance of reservoir systems. Higher dimensionality facilitates the separation of originally inseparable inputs by reading out from a larger set of spatiotemporal features of inputs. Moreover, memristor-based reservoirs either use multiple pulse rates, fast or slow read (immediately or with a delay introduced after the end of the sequence), or excitatory pulses to enhance the dimensionality of reservoir states. This adds to the complexity of the reservoir system and reduces power efficiency. In this paper, we demonstrate the first reservoir computing system based on a dynamic three terminal solid electrolyte ZnO/Ta2O5 Thin-film Transistor fabricated at less than 100°C. The inherent nonlinearity and dynamic memory of the device lead to a rich separation property of reservoir states that results in, to our knowledge, the highest accuracy of 94.44%, using electronic charge-based system, for the classification of hand-written digits. This improvement is attributed to an increase in the dimensionality of the reservoir by reading the reservoir states after each pulse rather than at the end of the sequence. The third terminal enables a read operation in the off state, that is when no pulse is applied at the gate terminal, via a small read pulse at the drain. This fundamentally allows multiple read operations without increasing energy consumption, which is not possible in the conventional two-terminal memristor counterpart. Further, we have also shown that devices do not saturate even after multiple write pulses which demonstrates the device’s ability to process longer sequences.

We demonstrate a novel concept for low power compute-in-memory applications in a room temperature fabricated ZnO/Ta 2 O 5 thin film transistor. By writing during the off-state, the device power consumption is reduced to nW despite a large L/W ratio. A thinner gate insulator thickness gives higher on/off ratio, nevertheless this reduces the retention time. The on/off ratio in the thicker oxide can be improved by asymmetric voltage pulses of higher magnitude in the off state without affecting power consumption. Benchmarked against other ReRAM devices, the device shows a competitive 8 nJ per transition, which allows a reduction in power consumption compared to a filamentary device. Such non-filamentary devices have closer similarity to biological synapses on account of slow operating speed.INDEX TERMS Tantalum oxide, zinc oxide, oxygen vacancies, memory TFTs and compute-in-memory.

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