In this paper, a VLSI architecture of a reducedcomplexity K-best sphere decoder is designed, which aims to solve the 4 × 4 64-QAM multiple-input multiple-output (MIMO) signal detection problems in high-speed applications. We propose a fully-pipelined sorter, which can generate one result per clock cycle and thus greatly enhance the detection throughput. On the other hand, various K values are adopted at each layer to save the hardware complexity. The proposed design has been implemented in 0.18 μm CMOS technology and has 366K gates. From post-layout simulation, this work achieves a detection rate of 1.5 Gbps at 62.5-MHz clock frequency.

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In this paper, a novel look-ahead technique taking advantages of the signal diversity is proposed to improve the performance of the conventional K-best sphere decoding algorithm that solves the MIMO detection problem of the spatial multiplexing scheme. We also examine the complexity overhead and the performance gain. Simulation results demonstrate that our proposed algorithm can achieve better performance with lower complexity by using a smaller K value than the one used in the conventional K-best algorithm.Index terms -MIMO, sphere decoder, K-best.I.

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