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A facile sol–gel spin coating method has been proposed for the synthesis of spin-coated ZnO nanofilms on ITO substrates. The as-prepared ZnO-nanofilm-based W/ZnO/ITO memory cell showed forming-free and tunable nonvolatile multilevel resistive switching behaviors with a high resistance ratio of about two orders of magnitude, which can be maintained for over 103 s and without evident deterioration. The tunable nonvolatile multilevel resistive switching phenomena were achieved by modulating the different set voltages of the W/ZnO/ITO memory cell. In addition, the tunable nonvolatile resistive switching behaviors of the ZnO-nanofilm-based W/ZnO/ITO memory cell can be interpreted by the partial formation and rupture of conductive nanofilaments modified by the oxygen vacancies. This work demonstrates that the ZnO-nanofilm-based W/ZnO/ITO memory cell may be a potential candidate for future high-density, nonvolatile, memory applications.

In this paper, the effect of nitrogen annealing on the resistive switching characteristics of the rutile TiO2 nanowire-based W/TiO2/FTO memory device is analyzed. The W/TiO2/FTO memory device exhibits a nonvolatile bipolar resistive switching behavior with a high resistance ratio (RHRS/RLRS) of about two orders of magnitude. The conduction behaviors of the W/TiO2/FTO memory device are attributed to the Ohmic conduction mechanism and the Schottky emission in the low resistance state and the high resistance state, respectively. Furthermore, the RHRS/RLRS of the W/TiO2/FTO memory device is obviously increased from about two orders of magnitude to three orders of magnitude after the rapid nitrogen annealing treatment. In addition, the change in the W/TiO2 Schottky barrier depletion layer thickness and barrier height modified by the oxygen vacancies at the W/TiO2 interface is suggested to be responsible for the resistive switching characteristics of the W/TiO2/FTO memory device. This work demonstrates the potential applications of the rutile TiO2 nanowire-based W/TiO2/FTO memory device for high-density data storage in nonvolatile memory devices.

In this study, a class of Generalized Low-Density Parity-Check (GLDPC) codes is designed for data transmission over a Partial-Band Jamming (PBJ) environment. The GLDPC codes are constructed by replacing parity-check code constraints with those of nonsystematic Bose-Chaudhuri-Hocquenghem (BCH), referred to as Low-Density Parity-Check (LDPC)-BCH codes. The rate of an LDPC-BCH code is adjusted by selecting the transmission length of the nonsystematic BCH code, and a low-complexity decoding algorithm based on messagepassing is presented that employs A Posteriori Probability (APP) fast BCH transform for decoding the BCH check nodes at each decoding iteration. Simulation results show that the LDPC-BCH codes with a code rate of 1/8.5 have a bit error rate performance of 1 10 6 at signal-noise-ratios of 6.97 dB, 4.63 dB, and 2.48 dB when the fractions of the band jammed are 30%, 50%, and 70%, respectively.