This paper presents circuit techniques to improve write and read capability for dual-port SRAM design fabricated in a 45nm low-power process. The write capability is enhanced by negative write biasing without any reduction in the cell current for the other port. The result shows 12% better improvement with just 1.9% area overhead. This technique has been verified successfully on 65nm and 45nm SRAM chip and improved 120mV lower at 95% yield of minimum operation voltage than a conventional one. The read capability is enhanced by cell current boosting and word line voltage lowering schemes. The SNM is also enhanced significantly. The target is to work below 0.8V with the worst process corner variation.

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The electrochemical properties of various cleaning reagents of high, medium or low pH values for post Cu CMP cleaning and their interaction mechanisms with Cu surfaces were studied. Results showed that for the Cu in TMAH (pH=ll) a reverse reaction, Cu re-deposition, was also observed although the Cu was easier to corrode due to its more negative corrosion potential in this solution. Because of this abnormal Cu re-deposition, Cu anode and cathode reactions were found to occur at the same Cu islands, where the Cu were corroded and then re-filled by redeposition to form hollow defects. These defects were extremely difficult to detect by in-line defect inspection tools during wafer processing and can only be identified by FA after WAT failures. Careful examinations of electrochemical properties revealed that hump in the I-V curve is the key to this abnormities and a novel solution was proposed and developed to eliminate these defects.

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