The Advanced Encryption Standard (AES) issued by the National Institute of Standards and Technology in 2001 has become the new widely-used symmetric block cipher standard. A lot of efforts have been made on the various hardware implementations of the AES algorithm. Some focus on achieving low-cost constructions, while others focus on designing high throughput. Given the specific requirement of wireless communication and portable devices, this article presents an AES IP core with an acceptable trade-off between performance and area. By introducing composite fields Sboxes and researching optimization of MixColumn can reduce resources. The AES IP is designed based on Avalon bus. It is compatible with five modes including ECB, CBC, OFB, CFB, and CTR. 128,196,256 bits key are also supported. Meanwhile, it can be flexibly configured according to the specific circumstances. This design and implementation of the AES core has a certain value for the generalization the wireless communication terminal hardware platform.

Solid-state drives (SSDs) are replacing hard-disk drives (HDDs) because of their advantages of light weight, low power, and high speed. A flash translation layer (FTL) is a key to achieving a high efficiency in accessing an SSD. This letter presents an architecture to implement the mapping between the logical address and the physical address as hardwired to reduce the workload of the FTL inside an SSD.