Light emitting diodes (LEDs) and Si-based metal oxide semiconductor field effect transistors (MOSFETs) were monolithically merged in a single chip which consisted of a Si layer and an InGaPN/GaPN double heterostructure layer lattice-matched to Si grown on a Si substrate by dislocation-free growth process for the first time. The developed fabrication process was conformed to a conventional planar MOSFET process. All LEDs and MOSFETs operated normally. Light emission from the LED was modulated by switching the MOSFET. The growth and fabrication technologies could be effective for realizing monolithic optoelectronic integrated circuits for massively parallel processing and optical interconnections.

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A Si/III–V–N alloys/Si structure was grown on a Si substrate by solid‐source molecular beam epitaxy (SSMBE) with an rf plasma nitrogen source and electron‐beam (EB) evaporator. A two‐dimensional (2D) growth mode was maintained during the growth of all layers. High‐resolution X‐ray diffraction (HRXRD) revealed that the structure had a small lattice mismatch to the Si substrate. InGaPN/GaPN double‐heterostructure (DH) light‐emitting diodes (LEDs) were fabricated on Si/III–V–N alloys/Si structure. The various sized LEDs were fabricated to put into the MOSFET for monolithic optoelectronic integrated circuits (OEIC). The luminescence properties of LEDs were evaluated by electroluminescence (EL). A double emission peak from all LED samples was observed at about 642 nm and 695 nm at room temperature (RT). As injection current increased, the emission peak wavelength changed from the peak wavelength of the InGaPN layer to that of the GaPN layer, likely due to carrier overflow of the active layer. A simplified fabrication process for the microsize LED of the unit circuit was proposed. The LEDs with emission areas from 5 × 5 μm2 to 20 × 20 μm2 were fabricated. The LED with an emission area of 5 × 5 μm2 can be applied to an optical device of a monolithic OEIC. (© 2007 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

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Optoelectronic integrated circuits (OEICs) have been expected for realization of novel devices and circuits. It is necessary for realization of OEICs to combine Ill-V compounds and Si with high quality. However, many dislocations were induced by the large difference in valence electron and lattice-constant between Ill-V compounds, such as GaAs and InP, and Si. We have already realized a dislocation-free and lattice-matched Si/GaPN/Si using molecular beam epitaxy (MBE)[1]. In addition, a dislocation-free InGaPN/GaPN double hetero (DH) light emitting diode (LED) has been realized on a Si substrate [2]. If these technologies are merged systematically, the top Si layer and III-V-N alloys will be used for integrated circuits and optical devices, respectively, as shown in Fig. 1 [3]. In this study, we have investigated a fabrication process for monolithic OEICs based on Si/III-V-N/Si structure and realized MOSFETs and LEDs in the same Si/III-V-N/Si wafer.A Si/III-V-N/Si wafer was grown by MBE, as shown in Fig. 2. A p-Si(100) substrate misoriented 40 toward [011] direction with carrier concentration of 5x1 OI8cm3 was used as a substrate. A GaP layer grown by migration enhanced epitaxy (MEE) is necessary to solve the difference in valence electron between Si and Ill-V compound semiconductors. An InyGa1-yPO.96No.04/GaPo.98No.o2 DH structure was grown at 500°C in the III-V-growth chamber. The GaP098N002 layers are lattice matched to Si.InyGa1 yP0.96No.04 layer is an active layer for DH LEDs. After the growth of DH structure, a thermal treatment was performed at 450°C and the sample was transferred to the Si-growth chamber through a vacuum chamber. A 1 ptm-thick Si layer was grown by electron-beam evaporator on the n-GaPN layer.A carrier concentration in the Si epilayer of 4x1017cm-3 was measured by four-point probe method.A fabrication sequence is proposed in Fig. 3. A 1ptm-thick field-oxide layer was deposited by chemical vapor phase deposition after separating LED regions by reactive ion etching. For simplicity of the process, a thermal annealing to increase the luminescence efficiency and a post-annealing of ion-implantation were combined with a gate-oxidation process. The luminescence of GaPN layers has been increased by the annealing at 900°C for 1-10min [4]. Thus, gate-oxidation was performed at 900°C for 10min in a wet 02 ambient, since a growth rate is higher than that in dry oxidation. Figure 4 shows a micrograph of a chip fabricated through the OEIC process. pMOSFETs and LEDs are shown in the same chip. Capacitance-voltage characteristics of MOS diodes showed surface inversion. The thickness of gate oxide was estimated at 16nm, which was close to a thickness of oxide grown on a bare n-Si wafer as a reference. The carrier concentration was estimated at 6.6x1 017cm-3.The wet oxidation was found to be utilized for the OEIC process. Figure 5(a) shows typical characteristics of drain currents(IdS) versus drain voltages(Vd,). Although a threshold voltage of -3. 1V was relatively high, the pMOSFET characteristics have ...