This paper presents an analytical model for CMOS The amount of decap required for proper circuit logic propagation delay which includes the effect of power operation will be a function of how much current that gate or supply noise. Using the nth power law model of MOSFETs, latch, as well as gates and latches around it, is drawing from two scenarios are addressed: self-induced power supply noise the power supply and return networks. Therefore, the and globally-induced power supply noise. The analytical designer must be able to quantify the relationship between model is verified in simulation for both cases. The self-induced circuit performance aspects, such as propagation delay, with noise model matches simulation to within 0.36%. The globallychanges in power supply. Using this relationship, a induced noise model matches simulation to within 5% for maximum perturbation in supply voltage, and thus a typical input rise time values and never more than 15% under decoupling capacitor size, can be calculated. This technique extreme conditions. extreme conditions.combined with a layout based technique will provide the designer with a truly optimized decap sizing and placement. INTRODUCTIONThis paper quantifies the relationship between supply With the continued scaling of device sizes, higher levels voltage noise and propagation delay. This will provide the of integration, and ever increasing clock speeds, the designer, and eventually an automated decap placement inductive and resistive components of power and ground algorithm, with the proper information to optimize decap interconnects become non-negligible in terms of apparent size and placement through the early stages of the design supply voltage seen by logic gates during logic transitions.process. Section II describes the model derivation. Section In the case of highly integrated, high speed digital CMOS III discusses simulation results. Section IV includes a systems, the resistive and inductive components of the power conclusion and discussion on future work. and ground interconnects leads to a momentary decrease in supply voltage while multiple gates switch simultaneously.II. PROPAGATION DELAY MODEL This has several effects on the circuit under question. First, the propagation delay between input and output is increased.Sakurai and Newton's MOSFET model, the nth power This issue has been studied in [1] through static timing law model [4], is frequently used in calculation of CMOS analysis. Second, through the lowering of supply voltage propagation delays. It is computationally wieldy and the noise margin of the gate is reduced. This reduced noise includes short channel MOSFET effects making it very margin allows for the possibility of incorrect logic applicable to mode, scaled technologies. One of the transitions.downfalls of the Sakurai-Newton model, however, is that the parameters it uses are empirically derived from simulation or The general solution to reducing this power supply noise device data. There has been some work done in [5] to is to add local decoupl...

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