An ASIC-Ready 1.25&amp;#x2013;6.25Gb/s SerDes in 90nm CMOS with multi-standard compatibility

Nishi, Y.; Abe, Katsumasa; Ribo, J.; Roederer, B.; Gopalan, A.; Benmansour, M.; Ho, A.; Bhoi, Akash Kumar; Konishi, Masami; Moriizumi, R.; Pathak, V.; Gondi, S.

doi:10.1109/asscc.2008.4708723

2008 IEEE Asian Solid-State Circuits Conference 2008

DOI: 10.1109/asscc.2008.4708723

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An ASIC-Ready 1.25–6.25Gb/s SerDes in 90nm CMOS with multi-standard compatibility

Y. Nishi

Katsumasa Abe

J. Ribo

et al.

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Cited by 7 publications

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A 19 mW/lane Serdes transceiver for SFI-5.1 application

Fallahi

Cui

et al. 2011

2011 IEEE Custom Integrated Circuits Conference (CICC)

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An ASIC-Ready 1.25–6.25Gb/s SerDes in 90nm CMOS with multi-standard compatibility

Cited by 7 publications

References 7 publications

A 19 mW/lane Serdes transceiver for SFI-5.1 application

A 19 mW/lane Serdes transceiver for SFI-5.1 application

A new time-based architecture for serial communication links

12-Gb/s low-power voltage-mode driver for multi-standard serial-link applications

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