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An evaluation of the architecture-level power estimation simulator, ESP (Early design Stage Power and performance simulator), is presented. With ESP, it is possible to accomplish more efficient design by using the architecture-level and gate-level simulator correctly. The estimation and the actual measured results are very similar. In addition, the accuracy of ESP has been improved by 18.3%. IntroductionAn architecture-level power estimation simulator, ESP, has been developed[l], and applied t o an RISC processor design for PDA use [2].In the early design stages, a precise estimation of the power dissipation is not always necessary. A fast architecture-level estimate is more useful for making early design decisions. As the design work progresses, a great deal of accuracy in the power estimation is increasingly required. Because of the long turn around time for gate-level simulation, simulation at the gatelevel only for major components and the architecturelevel for the whole circuit is more efficient.For these reasons, we have evaluated the accuracy of

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