A new method, called gate current Random Telegraph Noise (I G RTN), was developed to analyze the oxide quality and reliability of high-k gate dielectric MOSFETs. First, a single electron trapping/detrapping from process induced trap in nMOSFET was observed and the associated physical mechanism was proposed. Secondly, I G RTN has also been successfully applied to differentiate the difference in electron tunneling mechanism for a device under high-field or low-field stress. Finally, the softbreakdown (SBD) behavior of a device can be clearly identified. Its I G RTN characteristic is different from that before soft-breakdown. It was found that SBD will indeed induce extra leakage current as a result of an additional breakdown path.

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A novel technique to profile the spatial distribution of interface and bulk traps in high-k gated MOSFETs from a low leakage charge pumping technique, has been demonstrated in nMOSFETs with high-k gate dielectric. Both interface traps (fast traps) and bulk traps (slow traps) show their respective impact on the device reliability. The spatial distribution of interface traps and high-k bulk traps in two dimensions can be separated. Applications to the understanding of the mechanisms in interface/bulk traps generation after PBTI stress have also been addressed.