Resistivity is observed quantitatively in a thin electroplated copper layer. A resistivity of 2.6 µΩ·cm is observed in a 600-nm-thick as-deposited copper layer by conventional electroplating. This resistivity increases rapidly with decreasing thickness and reaches 7.8 µΩ·cm at a thickness of 75 nm. This rapid increase is mainly due to the increase in the orientation ratio of the copper (111)/(200). The resistivity in the as-deposited layer is maintained at 2.2 µΩ·cm in a 75 nm low resistivity layer with a low orientation ratio. Such a low-resistivity thin layer is electroplated practically by newly developed process. The preparation of a low-stress seed layer is also required in this electroplating process.

No abstract

The properties of copper conductive layers electroplated from a copper hexafluorosilicate electrolytic solution have been studied. The observed resistivity is in the region of 2.9 ⍀ cm for an as-deposited copper layer electroplated from a conventional copper sulfate electrolytic solution. By electroplating from a copper hexafluorosilicate electrolytic solution on a low stress seed layer, a copper conductive layer with a larger grain size and lower stress can be obtained. A resistivity of 1.85 ⍀ cm can be attained for such an as-deposited layer. This resistivity is much lower than the 2.8 ⍀ cm of other as-deposited layers by conventional copper electroplating.

The effect of the stress and grain size of the seed layer deposited on TaN and Ta/TaN barrier films on the properties of electroplated copper interconnection layer is described. Properties such as resistivity and grain size are studied. The effect of chemicals employed for electroplating the copper layer is also studied after deposition on these seed layers. A lower resistivity copper layer can be obtained by reducing stress and by growing grain size in the seed and interconnection layers.Reduction of layer resistance is required in the manufacturing of multilevel Cu interconnection for logic devices to reduce the resistance-capacitance ͑RC͒ time constant in the interconnection line and circuits. Enhancement of the speed in this circuit and solving the problems due to stress generated during multilevel process are needed. Only a few works are reported for the deposition and manufacture of a low resistance interconnection layer. 1 Since the interconnection layer is surrounded with a thick high resistivity barrier layer, a narrow cross-sectional area is obtained for low resistivity Cu interconnects for р100 nm technology node. Resistance of such a narrow line is so high in some cases that it is close to that of aluminum interconnection layer resistance. There are no advantages in such an interconnection layer other than that of better electromigration resistance. Recently, it was reported that resistance of a Cu interconnection layer is largely affected by the barrier layer and seed layer parameters. 2,3 However, there is little interest in lowering of layer resistance by optimization of barrier and seed layers and their relationship. Manufacturers mostly concentrate on self-annealing effects and conformability of deposition. Therefore, higher effective resistance layers than those of conventional aluminum interconnections are being obtained for very small feature sizes.Resistivity of an electroplated Cu layer has been reported as being determined mainly by the grain size and stress of this layer rather than due to impurities in the layer and self-annealing. Grain size of the electroplating Cu is determined mainly by the stress and orientation of the Cu seed layer employed for electroplating. 4 To deposit or fabricate a low resistance Cu interconnection layer, correlation of the resistivity with many other parameters must be obtained. In this paper, We describe the effect of stress and grain growth in the seed and electroplated layer on the resistivity in the interconnection layer. A lower resistivity Cu layer has been deposited employing the use of a newly developed electrolytic solution of Cu hexafluorosilicate ͑CHS͒. 1

No abstract