This paper presents a cryogenic 8-bit 32 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) which operates down to 4.2 K. This work uses a modified liquid helium temperature (LHT) SMIC 0.18 μm CMOS technology to support the post-layout simulation. The proposed architecture adopts an offset-promoted dynamic comparator, waveform shaping circuit and true single-phase clock (TSPC) based sar logic circuit to achieve high realizing frequency and low power dissipation. At 1.8-V supply, 1.7 V input amplitude and 32 MS/s sampling frequency, the ADC achieves a power consumption of 2.4 mW and a signal-to-noise and distortion ratio (SNDR) of 47.7 dB, obtaining a figure of merit (FOM) of 378 fJ/conversion-step. The layout area of the ADC is about 0.253 mm2.

A novel power-efficient analog buffer at Liquid Helium Temperature (LHT) is proposed. The proposed circuit is based on an input stage consisting of two complementary differential pairs to achieve rail-to-rail level tracking. Results of simulation based on SMIC 0.18µm CMOS technology show the high driving capability and low quiescent power consumption at cryogenic temperature. Operating at single 1.4 V supply, the circuit achieves a slew-rate of +36 V/µs and -33.8 V/µs for 10 pF capacitive load. The static power of the circuit is only 55.7µW.

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