A scheme for testing SRAMs is proposed with a tester circuit consisting of SRAM-based reconfigurable cells. We first show an approach to reduce the number of reconfigurable cells required for the tester circuit. We then propose a tester for a 4-Mbit SRAM with reconfigurable cells of 16-bit data SRAMs. We also report the implementation of the proposed circuit. Four 16-bit reconfigurable cells, each of which consists of an SRAM and two CPLDs, were implemented, and mounted on a board. We confirmed that the tester functions correctly by performing a marching test. keywords: SRAM test, SRAM-based reconfigurable cell, memory tester, marching test

&straQ -A Distributed Globally ReplaceableRedundancy (DGR) scheme has been developed, which realizes a higher optimization of trade-off between yield and chip size. A newly developed yield simulator has demonstrated the effectiveness of the DGR scheme.