Sub-resolution assist features (SRAFs) provide an absolutely essential technique for critical dimension (CD) control and process window enhancement in immersion lithography. The selection of SRAF's size and placement are vital. 28nm node requires stringent CD control for active area (AA) layer. Since both AA line CD and space CD control are important, not only scattering bar (SB) but also reverse scattering bar (RSB) is used to improve AA litho process window. SB is used to improve line pattern process window, meanwhile RSB is implemented to improve space pattern process window as space CD shrinks as small as possible to meet design rule requirement. The main challenges of SRAFs are the proper SRAF size, right SRAFs placement, and avoiding SRAFs printing issue. SRAF size needs to balance process window and SRAF printing issue. Further more, mask making feasibility is also considered. 28nm AA lithography SRAFs rule simulation study with FDTD is used to optimize the AA litho process. 28nm AA test vehicle with SB and RSB size split and location split is designed to determine the integrated SRAFs solution. After implement thorough considered SRAFs rule, 28nm AA litho through pitch line and through pitch space process window can meet manufacturing specification.

Achieving good gate’s critical dimension uniformity (CDU) is very challenging since the CDU has shown not only high sensitivities to the variations in resist track recipe, scanner hardware and control, and etcher condition, but also have high correlation to the feature shape and pattern environment. For process generations at 28 nm half pitch, more aggressive CDU requirement will result in a push of OPC, reticle making and litho process to their limits. To more systematically analyze the linewidth variation and to find a viable solution to achieve required linewidth uniformity, we constructed linewidth variation budget, which includes variations in lithographic process, mask linewidth, optical proximity correction (OPC) error, and scanner control. Through analyzing the CDU requirement from process integration needs and referencing the ITRS roadmap’s recommendation, we have identified key budget contributors, which are OPC and mask making. In this paper, we will demonstrate our achievement in linewidth uniformity improvement.

It is known that critical dimension (CD), overlay, and defect are the three most crucial factors for Semi-conductor manufacture. Overlay control is especially important for Gate layer. In this paper we will focus on how to control overlay performance. Simulation will be carried out to optimize under-layer films to optimize the alignment signal strength, or the ASML’s unit: wafer quality (WQ). A solid alignment can ensure a good overlay control. Mask registration can also affect overlay performance markedly which is a new learning at 28nm tech node. A simple error distribution from metrology measurement angel will be made to discuss the effect of mask registration to overlay performance. KLA SOV (sources of variation) tool will be used to trace the error sources and analyze how much they each contribute to the total overlay error. Finally, a specification on mask registration error is built based on this analysis. Through these improvements, ITRS referred overlay specification is achieved on ASML immersion scanner. We believe that with high order function turned on, even better overlay performance will be achieved which could meet the manufacturing tolerances for the 28nm technology node.

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