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This paper presents a simple architecture for clock-fault detection in high-speed applications. The overall principle consists in converting a possible error of time to a logic voltage level. When a high voltage level is present at the output, a reliable clock is detected whereas a low voltage level implies a clock error. This detection system is intended for all System-on-Chip such as microcontrollers which use external clock from 4 MHz to 50 MHz. The proposed circuit is realized in CMOS 40 nm process technology. Simulation results prove the suitability of the structure and its integration on silicon is strongly considered by clock error detection in integrated circuits.

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