Flexible low-cost RFID/NFC tags have great potential to be embedded in everyday objects providing them a unique identifier or sensor readout facilitating the Internet-of-Everything, whereby a smartphone or tablet is the interface to the Internet-of-Things. The main challenge for flexible metal-oxide RFID tags is to fully comply with the ISO14443-A NFC standard to enable readout by standard NFC reader or handheld devices, due to the limited charge carrier mobility of the semiconductor and multiple sources of parameter variation caused by roughness, temperature and dimensional stability of the foils. Recent work by various groups [1][2][3][4] demonstrated only an incremental improvement in data rates from 50b/s to 396.5kb/s to be compatible with ISO14443 (105.9kb/s). In this work, we present a flexible metal-oxide NFC chip that is compliant with ISO14443-A, showcasing advancements on memory size, power consumption and a clock generation circuit.The flexible self-aligned metal-oxide transistor technology is shown in Fig. 15.2.1. The semiconductor is Indium-Gallium-Zinc-Oxide (IGZO) resulting in n-type thinfilm transistors (TFTs) exhibiting a mobility of 13.49cm²/Vs. The cross-section details a scalable self-aligned transistor architecture with channel lengths down to 2 and 1.5μm, and polyimide as flexible substrate. The gate insulator is 100nm SiO 2 . 400nm SiN x serves as decoupling layer between the metallization layers to decrease the parasitic overlap capacitors and acts as doping layer for the semiconductor area, which is not covered by gate dielectric. The local V T variability of 2μm self-aligned TFTs on flex is 150mV (Fig. 15. 2.1).The ISO14443-A specification describes a bit representation with data rates of 105.9kb/s (13.56MHz carrier divided by 128), Manchester encoding and OOK subcarrier modulation with a clock of 847.5kHz (carrier divided by 16). The logic gate delay to enable clock division is targeted around 10× of the carrier frequency, being 7.37ns. The spec on gate delay is studied by integrating unipolar n-type, pseudo-CMOS inverters [5] into 19-stage ring oscillators. The effect of channel length scaling on the inverter performance is plotted in Fig. 15.2.2, resulting obtained stage delays of 63.4ns for L=5μm and 5.2ns for L=2μm at 5V VDD and 10V VBIAS. In addition, the transistor ratios of the VBIAS branch have been adapted featuring a faster implementation of the pseudo-CMOS inverter (L2F and L1.5F). This reduces the stage delay down to 2.36ns at 5V VDD and 10V VBIAS for the 1.5μm version. Figure 15.2.2 shows that this logic implementation meets the specification for all VDD variations, yielding a more robust division circuit. The clock division circuit is based on negative edge-triggered flipflops. Figure 15.2.2 depicts also the measured clock division range for VDD varying between 3V to 5V. As expected, the 1.5μm fast implementation can divide a 13.56MHz signal over this supply range, with a maximum operating frequency of 27.3MHz.The drawback of channel length scaling without decreasing the...

Metal-Oxide thin-film transistors (TFTs) present unique opportunities to develop robust, low-cost and transparent electronics that can mechanically endure on flexible and stretchable substrates over large area in an industry compatible technology. Analog to digital converters (ADC) are an essential part of the Internet-of-Everything, where a multitude of sensing applications are envisaged, such as temperature and pressure sensor tags on human skin. In this work, dual-gate InGaZnO TFTs (IGZO) are demonstrated to achieve a 6-bit successive approximation (SAR) C-2C ADC operated at a clock of up to 400Hz and a power dissipation of 52.2µW at a power supply of V dd =15V. The ADC achieves a differential nonlinearity (DNL) of 0.7LSB and an integral nonlinearity (INL) of 0.58 LSB using only n-type TFTs. A figure of merit (FoM) of 66.7nJ/c.s. is achieved from an ADC on flexible substrate.

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