A balanced voltage-controlled oscillator (VCO) is designed and implemented in a 0.13 lm CMOS 1P8M process. The designed VCO circuit topology is an all nMOS LC-tank Clapp VCO using a series-tuned resonator. At the supply voltage of 0.5 V, the output phase noise of the VCO is À108.69 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 17.72 GHz, and the figure of merit is À186.84 dBc/Hz. The core power consumption is 4.2 mW. Tuning range is about 3.32 GHz, from 17.55 to 20.87 GHz, while the control voltage was tuned from 0 to 1.3 V.

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A diode-ring coupling technique has been used to design quadrature voltage-controlled oscillators (QVCOs), which consist of two n-core VCOs. The proposed CMOS QVCOs have been implemented with the TSMC 0.18 lm CMOS technology. A single-band and a dual-band QVCOs have been implemented to support the feasibility of the coupling technique. The die area of the single-band QVCO is 0.506 Â 0.905 mm 2 . At the supply voltage of 0.54 V, the total power consumption is 1.78 mW. The free-running frequency of the QVCO is tunable from 4.295 to 5.185 GHz as the tuning voltage is varied from 0.0 to 1.1 V. The measured phase noise at 1 MHz frequency offset is À114 dBc/Hz at the oscillation frequency 4.587 GHz, and the figure of merit of the proposed QVCO is À184.73 dBc/Hz.