Sound field renderings are data-intensive and computation-intensive applications. An alternative solution is to directly implement sound field rendering algorithms by using hardware. In this paper, a hardware-oriented finite-difference time-domain (FDTD) algorithm named HO-FDTD is proposed for sound field rendering, which has no complex operations involved, and consumes small hardware resources. In a sound space with 32,768 elements surrounded by rigid walls, the hardware simulation results are in good agreement with the software simulation results except for the one-cycle delay. In the software simulation, when the element scale is 32×32×32 and the time steps are 20,000, the HO-FDTD speeds up computations by 19% against the updated digital Huygen's model (DHM) and Yee-FDTD, and by 132% against the original DHM. Compared with the software simulation, the hardware systems with the parallel architecture and the time-sharing architecture enhance their calculation performance significantly in the case of different element scales, and provide a higher data throughput.

We do a numerical calculation on the quark-loop effects on the dressed gluon propagator in the chiral limit.It is found that the quark-loop effects on the dressed gluon propagator are significant in solving the quark propagator in the rainbow approximation of the Dyson-Schwinger equation. The approach we used here is quite general and can also be used to calculate both the chemical potential and current quark mass dependence of the dressed gluon propagator.

Real-time sound field renderings are computationally intensive and memory-intensive. Traditional rendering systems based on computer simulations suffer from memory bandwidth and arithmetic units. The computation is time-consuming, and the sample rate of the output sound is low because of the long computation time at each time step. In this work, a processor with a hybrid architecture is proposed to speed up computation and improve the sample rate of the output sound, and an interface is developed for system scalability through simply cascading many chips to enlarge the simulated area. To render a three-minute Beethoven wave sound in a small shoe-box room with dimensions of 1.28 m × 1.28 m × 0.64 m, the field programming gate array (FPGA)-based prototype machine with the proposed architecture carries out the sound rendering at run-time while the software simulation with the OpenMP parallelization takes about 12.70 min on a personal computer (PC) with 32 GB random access memory (RAM) and an Intel i7-6800K six-core processor running at 3.4 GHz. The throughput in the software simulation is about 194 M grids/s while it is 51.2 G grids/s in the prototype machine even if the clock frequency of the prototype machine is much lower than that of the PC. The rendering processor with a processing element (PE) and interfaces consumes about 238,515 gates after fabricated by the 0.18 µm processing technology from the ROHM semiconductor Co., Ltd. (Kyoto Japan), and the power consumption is about 143.8 mW.

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