For modern processes at deep sub-micron technology nodes, yield design, especially the design at the layout stage is an important way to deal with the problem of manufacturability and yield. In order to reduce the yield loss caused by redundancy material defects, the choice of nets to be optimized at first is an important step in the process of layout optimization. This paper provides a new sensitivity model for a short net, which is net-based and reflects the size of the critical area between a single net and the nets around it. Since this model is based on a single net and includes the information of the surrounding nets, the critical area between the single net and surrounding nets can be reduced at the same time. In this way, the efficiency of layout optimization becomes higher. According to experimental observations, this sensitivity model can be used to choose the position for optimization. Compared with the chip-area-based and basiclayout-based sensitivity models, our sensitivity model not only has higher efficiency, but also confirms that choosing the net to be optimized at first improves the design.

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Redundant via (RV) insertion is a useful mechanism to enhance via reliability. However, when extra vias are inserted into the design, the circuit timing might be changed. Therefore, how to insert RV under the timing constraints is the main challenge. In this paper, we introduce a new model to compute the distance between a RV and the corresponding single via, put forward a new RV type, which is called the long length via (LLV), and then present an improved RV insertion method considering the timing constraints. This computing model can certify that the timing, which is obtained after inserting a RV, is not greater than the original timing. Meanwhile, the new RV type LLV can increase the possibility of RV insertion; this method provides a global perspective for the RV insertion. Considering the timing constraints, the total redundant via insertion rate is 85.38% in the MIS-based method, while our proposed method can obtain a high insertion rate 88.79% for the tested circuits.