Tremendous effort has been made toward the development of high-density, low-cost, and nonvolatile solid-state storage devices for use in portable electronic devices such as MP3 players, mobile phones, and digital cameras. [1][2][3][4][5][6][7][8][9][10][11] Among the many types of nonvolatile memory technology, flash memory devices with discrete charge-trapping layers, such as silicon-oxide-nitrideoxide-silicon (SONOS) devices or nanocrystal (NC)-based memory devices, are of great interest to the electronics industry, because of their better endurance, smaller chip size, and lower power consumption compared with floating-gate devices. [12][13][14][15][16][17][18][19][20][21][22][23][24][25] Recently, Samsung Electronics successfully fabricated a 64-gigabit density SONOS-type flash memory device using Si 3 N 4 as a charge-trap layer.[26] However, it is very difficult to control the trap density and distribution in SONOS devices, although these parameters are quite important in determining the memory characteristics, especially the programmed/erased bit distribution and data retention. Thus, NC memory devices using metallic NCs as a charge-trapping layer have an advantage when it comes to controlling the trap density and distribution, because the density and location of the NCs can be controlled by adjusting the process parameters. Considerable work has focused on the controlled synthesis of semiconducting or metallic nanoparticles for use in nonvolatile memory devices. [16][17][18][19][20][21][22][23][24][25] Recently, we report that ordered arrays of metallic nanoparticles by a micellar route and multilayered metallic nanoparticles can be used as chargestorage media for nonvolatile memory devices with tailored performances. [24,25] However, most of the research on nanoparticle-based memory devices has been focused on the use of elemental metal nanoparticles as a charge trapping layer. Herein, we report for the first time the use of a controlled binary mixture of metal nanoparticles for the purpose of tuning the memory characteristics in charge-trap flash memory devices with i) a comparative and systematic study of the charging/discharging behaviors, ii) an analysis of the different charge trapping mechanisms according to the type of metal nanoparticle being used, iii) nanoscale device performance characterization using Kelvin force microscopy (KFM), and iv) tunable memory performances and applications to multilevel data storage. Figure 1 shows a schematic illustration of the memory architectures and storage element configurations. Elemental metal nanoparticles of Co and Au and a binary mixture thereof were used as the charge-trapping layers in the memory devices. A sputter-deposited HfO 2 layer was used both as a tunneling and blocking oxide layer. This type of device is based on the charge carrier transfer between the Si substrate and the charge trapping layer via the tunneling oxide (nominal thickness of 5 nm) by using a field effect. A thick blocking oxide layer (nominal thickness of 15 nm) is used to prevent ...

This study demonstrates that self-assembled diblock copolymer micelles can be used as a template to assemble cobalt (Co) nanocrystal (NC) arrays for use as charge storage layers in charge trap flash memory devices. Diblock copolymer micelles embedded with Co were synthesized on p-Si substrates having a thin tunneling oxide of HfO2. The micelle templates were completely removed by oxygen plasma treatment and reduction procedures, resulting in ordered arrays of Co NCs. The nonvolatile memory devices exhibit program/erase characteristics, as confirmed by their capacitance-voltage responses, current-voltage responses, endurance characterization, and nanoscale device measurement using scanning nonlinear dielectric microscopy.

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