This paper describes a fast received signal strength indicator (RSSI) circuit for wireless communication application. It is developed using a novel power detector with a fast settling time. The power detector is consisted of a variable gain amplifier (VGA), a peak detector, and a comparator in a closed loop. The VGA achieved a wide gain range in a closed loop form. For the peak detector, a fast settling time and small ripple are obtained using the orthogonal characteristics of quadrature signals. In 0.18μm CMOS process, the RSSI value settles down in 20μs with power consumption of 20mW, and the maximum ripple of the RSSI is 30mV. The proposed RSSI circuit is fabricated with a Personal Handy-phone System (PHS) receiver. The active area is 0.8mm × 0.8mm.

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This paper proposes class-E power amplifier including negative capacitance to optimize shunt drain capacitance. The negative capacitance improves efficiency, compensates for surplus shunt drain capacitance resulting from parasitic capacitance, and is implemented without an external circuit. A cascode single-ended class-E RF power amplifier including driver stage is fabricated using a 0.13-µm standard CMOS technology delivering 29 dBm with 66% drain efficiency and 63% poweradded efficiency at 1.8 GHz.

In this article, an internal, compact, multiband antenna for an USB dongle application is proposed. The designed antenna simultaneously satisfied the voltage standing wave ratio (VSWR) by less than 2:1 for the following applications and their respective frequency range bands: long-term evolution (LTE), range of 746 to 794 MHz; digital cellular network (DCN), range of 824 to 894 MHz; and personal communication system (PCS)-1900, range of 1850 to 1990 MHz.ABSTRACT: This article proposes an efficient power-combining architecture with differential and single-ended power amplifiers (PAs) in a CMOS process. The single-ended amplifier is added for overall efficiency enhancement. To demonstrate this concept, a CMOS PA using the proposed architecture was fabricated with a 0.13-lm CMOS technology that delivers 30.6 dBm of output power with 42% drain efficiency and 38% power-added efficiency at 1.95 GHz. Figure 5 Comparison of measured antenna gain and efficiency with and without ZOR. ---, Gain without ZOR; --, gain with ZOR; -Á -, efficiency without ZOR; and -, efficiency with ZOR