A high-temperature series for the spin-glass order-parameter susceptibility is presented for n-component spins on a &dimensional hypercubic lattice. The coupling between neighbouring spins is taken to be a Gaussian random variable. The series is analysed for the cases of XY (n = 2) and Heisenberg (n = 3) spins. In each case the transition temperature falls to zero near four dimensions, indicating that there is no Edwards-Anderson order in less than four dimensions.

Pt/(Ba, Sr)TiO 3 /Pt capacitors fabricated by sputtering technique showed abnormally higher leakage current when negative bias was applied to the top electrode. In this letter, two kinds of processes were attempted to reduce high leakage current of Pt/BST/Pt capacitors for dynamic random access memory devices: (1) postannealing under O2 atmosphere and (2) adding oxygen into sputtering gas of platinum top electrode. These processes were very effective to reduce the oxygen vacancy in the BST films which are mostly responsible for such a high leakage current. The higher reverse currents were significantly lowered by these processes, so that we could obtain symmetric current versus voltage curves of Pt/BST/Pt capacitors.

Pt/(Ba, Sr)TiO3/Pt capacitors were fabricated on TiN/Ti/ Poly–Si/SiO2/Si substrate by sputtering technique and effects of post-annealing conditions on the current vs. voltage ( I–V ) characteristics of the capacitors were investigated. It was found that leakage currents of Pt/BST/Pt capacitors were greatly depended on the annealing sequence as well as annealing atmosphere. BST films annealed under Ar/H2 or N2 showed much higher leakage current than as-deposited films regardless of the fabrication of top electrode. On the contrary, annealing under O2 atmosphere was effective to reduce leakage currents of the BST films if annealing process was carried out after fabrication of top electrode. Leakage current of Pt/BST(50 nm)/Pt capacitors annealed under O2 atmosphere at 500° C for 1 h after fabrication of Pt top electrode was 5×10-7 A/cm2 even at 7 V. In this work, effects of annealing conditions on the I–V properties of Pt/BST/Pt capacitors were explained with energy band diagram in which oxygen vacancies play a key role.

P-doped SiGe films were deposited and characterized in terms of their electrical and mechanical properties. Si 1Ϫx Ge x with x ϭ 0.6-0.8 was deposited with deposition rates of 70-100 Å/min at 450-550°C. Films with Ge content of Ͻ70% showed a very low etch rate in H 2 O 2 at 90°C; the etch rate increased significantly for higher Ge content. The resistivity of as-deposited films was about 0.1 ⍀ cm and could be lowered to 5 ϫ 10 Ϫ3 ⍀ cm after annealing at 900°C. The films exhibited compressive residual stress of up to 270 MPa. After annealing at Ͼ600°C, the stress changed to 100-200 MPa tensile due to the intrinsic stress relief and the thermal expansion difference between the films and the silicon substrate. In a cantilevered beam, the stress gradient through the film thickness made the as-deposited films curl downward. The stress could be reduced with appropriate annealing. With optimized deposition and annealing conditions, n-type SiGe microelectromechanical systems structures were fabricated to show feasibility of their integration with underlying multilayer poly-Si microstructures.Microelectromechanical systems ͑MEMS͒ are gathering growing attention and their application to inertial sensors, 1-3 displays, 4 and optical switches 5,6 has been successfully demonstrated. Surface micromachining, one of the core technologies for MEMS, is based on the selective etching of patterned stacks of sacrificial and structural thin films to form freestanding microstructures. Polycrystallinesilicon ͑poly-Si͒ structural layers and oxide sacrificial layers are the most commonly used materials for surface micromachining and are the basis of MEMS foundry processes. 7,8 The materials and processes for poly-Si surface micromachining are those of the semiconductor industry, a significant advantage for commercialization.The deposition and annealing conditions for optimizing poly-Si as a structural material have been studied extensively. 9-11 The deposition temperature for structural poly-Si films is typically in the range of 580-600°C. However, in order to achieve low average residual stress and low stress gradient through the thickness of the film, anneals in excess of 1000°C are generally required. 12 These high temperature anneals can cause difficulties with wafer curvature, due to the large mismatch between the coefficient of thermal expansion of oxides (5 ϫ 10 Ϫ7 /K) and the silicon substrate (2.5 ϫ 10 Ϫ6 /K). For multilayer MEMS processes, which are useful for micro-optical component fabrication, the thin-film stacks of poly-Si and oxide layers can be over 10 m thick. 13 Poly-SiGe alloys have been investigated recently as a microstructural material. 14-17 The deposition temperature of these films using a conventional horizontal low-pressure chemical vapor deposition ͑LPCVD͒ process is in the range of 400-500°C. Furthermore, hydrogen peroxide at a temperature of 90°C selectively etches polySiGe alloys with Ge content higher than 70 atom %; 18 this allows Ge-rich alloys to replace oxide as the sacrificial layer. 17 In some cases, t...

Ir films deposited on polycrystalline silicon (poly-Si), with and without barrier layer, were annealed and the thermal stability was investigated to check the feasibility of the structure for bottom electrode of integrated ferroelectric capacitors. Ir did not form silicide up to 700 °C and did not get oxidized up to 550 °C. It was found that Ir prevented diffusion of oxygen through it when annealed at 700 °C. Ir/poly-Si is believed to be most promising for bottom electrode structure from the results.