As the complexity of high-performance microprocessor increases, functional veri cation becomes more and more difcult and RTL simulation emerges as the bottleneck of the design cycle. In this paper, we suggest C language-based design and veri cation methodology to enhance the simulation speed instead of the conventional HDL-based methodologies. RTL C modelStreC describes the cycle-based behaviors of synchronous circuits and is followed by model re ning and optimization using LifeTime AnalyzerLTA and Cleaner. The simulation speed of cycle-based C model makes it possible to test the RTL design with the real-world" application programs in the order-of-magnitude faster speed than the commercial event-driven simulators. Using the proposed functional veri cation methodology, HK486, an intel 80486 -compatible microprocessor was successfully designed and veri ed.