A C-based RTL design verification methodology for complex microprocessor

Abstract

As the complexity of high-performance microprocessor increases, functional veri cation becomes more and more difcult and RTL simulation emerges as the bottleneck of the design cycle. In this paper, we suggest C language-based design and veri cation methodology to enhance the simulation speed instead of the conventional HDL-based methodologies. RTL C modelStreC describes the cycle-based behaviors of synchronous circuits and is followed by model re ning and optimization using LifeTime AnalyzerLTA and Cleaner. The simulation speed of cycle-based C model makes it possible to test the RTL design with the real-world" application programs in the order-of-magnitude faster speed than the commercial event-driven simulators. Using the proposed functional veri cation methodology, HK486, an intel 80486 -compatible microprocessor was successfully designed and veri ed.

Checking architectural outputs instruction-by-instruction on acceleration platforms

“…However, acceleration-based flows usually have a coarse checking granularity, that is, they can label a test as passed or failed after its completion but, in case of failure, no additional information is available related to the time/location of the bug manifestation. Comparing architectural state between a purely software-simulated design model and a golden architectural software model at instruction boundaries, or at other synchronizing boundaries, has also been a commonly deployed method for microprocessor validation [14,5]. The key reason why this methodology has not yet been considered for acceleration, with the golden model running in software on a host platform, is that connecting these two components (golden model and accelerated design) is both difficult (due to lack of debugging support) and detrimental to performance [5].…”

Digital system simulation: methodologies and examples

“…At this level of simulation the simulator accurately models all the concurrency and resource contention in the system. The level of detail required to do this for the complexity of current chips makes RTL simulation slow even for the fastest simulators [22]. Despite their slow speed, RTL simulators are heavily used to check the correctness of the system.…”

“…Cycle based logic simulators which are also called levelized compiled code logic simulators rely on the synchronous nature of digital logic to eliminate all considerations of time that are smaller than a clock cycle. Cycle based simulators have the potential to provide much higher simulation performance than discrete-event simulators because they eliminate much of the run time processing overhead associated with ordering and propagating events [1,6,22]. Some cycle-based logic simulators dispense with the accurate representation of the logic between the state elements altogether and transform this logic to speed up simulation even further [15].…”

Verification of a microprocessor using real world applications

“…Verification very often takes up more than half of the whole design time for complex microprocessors [5]. Various design verification methodologies with the relevant environmental setup for an effective verification have been proposed and/or used now [1,2,3,4,5,6].…”

“…Verification very often takes up more than half of the whole design time for complex microprocessors [5]. Various design verification methodologies with the relevant environmental setup for an effective verification have been proposed and/or used now [1,2,3,4,5,6]. For the case of designing next-generation microprocessors, microcontrollers, and DSP processors which already have a large number of firmwares and application softwares running on them, the requirement on the backward compatibility with the previous products or the full compliance with all relevant softwares makes the verification process more and more difficult, error-prone and time consuming.…”