No abstract

Embedded processors are increasingly being used in digital consumer appliances such as cellular phones, digital still/video cameras, and car navigation systems. They must deliver high performance with reasonable area and power consumption and be flexible enough to meet a wide range of requirements for various applications. However, only a few devices targeting large markets, such as cellular phones, can bear the cost of a special-purpose processor design. An alternative is to use optional modules, such as DSPs and floating-point units (FPUs), to augment the capabilities of the basic processing core. An optional DSP can be added as an execution unit, which is much smaller than a full DSP core, to effectively accelerate standardized applications such as multimedia [1]. While PCs and game consoles can bear the high cost of special graphics hardware much larger than a processor core [2][3], other digital consumer appliances cannot. An optional FPU handles a wide dynamic range of data thus simplifying programming, especially for graphics acceleration. Therefore, an optional FPU is a good approach to achieve high graphics performance with an embedded processor [4]. A flexible SuperH TM (SH) processor core is developed to meet these requirements.The specifications of the SH processor core are shown in Fig. 18.5.1. The use of an on-chip RAM ensures real-time response, a key feature of embedded processors. Micrographs of the standard-version processor core and the first product chip for car navigation systems are shown in Fig. 18.5.2. A low power version is integrated in an application processor for cellular phones [5].

This paper presents an approach for high-quality builtin test using a neighborhood pattern generator (NPGJ. Proposed NPG is practically acceptable because ( a ) its structure is independent of circuit under test, (b) it requires low area overhead and no performunce degradation, and (c) it can encode deterministic test cubes, not only for stuck-at faults but also transition faults, with high probability. Experimental results for large industrial circuits illustrate the efficiency of the proposed approach.

No abstract

We built a 12.4 mm × 12.4 mm, 45-nm CMOS, chip that integrates eight 648-MHz general purpose cores, two matrix processor (MX-2) cores, four flexible engine (FE) cores and media IP (VPU5) to establish heterogeneous multi-core chip architecture. The general purpose core had its IPC (instructions per cycle) performance enhanced by adding 32-bit instructions to the existing 16-bit fixed-length instruction set and executing up to two 32-bit instructions per cycle. Considering these five-toseven years of embedded LSI and increasing trend of access-master within LSI, we predict that the memory usage of single core will not exceed 32-bit physical area (i.e. 4 GB), but chip-total memory usage will exceed 4 GB. Based on this prediction, the physical address was expanded from 32-bit to 40-bit. The fabricated chip was tested and a parallel operation of eight general purpose cores and four FE cores and eight data transfer units (DTU) is obtained on AAC (Advanced Audio Coding) encode processing.